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* Fixes for new part typesMiodrag Milanovic2020-07-081-8/+20
* ice40: Add fallback behavior for Extra Cell config bits vectorsSylvain Munaut2020-06-021-1/+11
* ice40: Add support for the 2nd bit of SHIFTREG_DIV_MODESylvain Munaut2020-06-021-1/+1
* ice40: Improve error handling of Lattice-style parametersDavid Shah2019-12-101-0/+3
* Major Property improvements for common and iCE40David Shah2019-08-051-29/+33
* clangformatDavid Shah2019-06-241-2/+3
* ice40: add RGB_DRV/LED_DRV_CUR support for u4kSimon Schubert2019-06-101-0/+7
* ice40: Add support for SB_I2C and SB_SPISylvain Munaut2019-03-251-0/+22
* ice40: support u4kSimon Schubert2019-02-231-1/+11
* ice40: Add PCF support for -pullup, -pullup_resistor and -nowarnDavid Shah2018-12-201-2/+15
* ice40: Improve bitstream error handlingDavid Shah2018-12-061-2/+10
* clangformatDavid Shah2018-12-061-1/+1
* ice40: Add support for placing SB_LEDDA_IP block.Daniel Serpell2018-12-011-1/+2
* ice40: Update the way LVDS inputs are handled during bitstream generationSylvain Munaut2018-11-281-48/+48
* ice40: Add support for SB_RGBA_DRVSylvain Munaut2018-11-191-0/+5
* ice40: Add support for SB_GB_IOSylvain Munaut2018-11-191-0/+1
* ice40: Add support for PLL global outputs via PADINSylvain Munaut2018-11-191-44/+50
* ice40: Introduce the concept of forPadIn SB_GBSylvain Munaut2018-11-191-1/+17
* ice40/bitstream: Handle IoCtrl.IE_ polarity when configuring unused SB_IOSylvain Munaut2018-11-191-2/+7
* ice40/bitstream: Convert to UNIX line endingsSylvain Munaut2018-11-161-1043/+1043
* ice40: Remove unnecessary RAM assertionDavid Shah2018-11-161-1/+0
* ice40: Don't set colbuf bits for 384David Shah2018-11-111-0/+2
* clangformatDavid Shah2018-09-301-4/+1
* ice40: LVDS input bitstream supportDavid Shah2018-09-241-4/+48
* do not break if there are no nets loaded from sym sectionMiodrag Milanovic2018-08-181-4/+6
* Get rid of PortPin and BelType (ice40, generic, docs)Clifford Wolf2018-08-081-17/+17
* API change: Use CellInfo* and NetInfo* as cell/net handles (common, ice40)Clifford Wolf2018-08-051-24/+24
* clangformatClifford Wolf2018-08-051-21/+22
* ice40: Bitstream gen for LUT permutationDavid Shah2018-08-041-8/+78
* ice40: Add bitstream gen for routethru LUTsDavid Shah2018-08-031-9/+58
* ice40: Add HFOSC support, force fabric routing on oscillators for nowDavid Shah2018-08-011-0/+4
* clangformatSergiusz Bazanski2018-08-011-2/+3
* clangformatEddie Hung2018-07-251-3/+2
* ice40: fixes before reviewSergiusz Bazanski2018-07-241-6/+6
* ice40: move PLL->IO from pseudo pip to second uphill belSergiusz Bazanski2018-07-241-15/+16
* ice40: emit list of upbels in chipdbSergiusz Bazanski2018-07-241-1/+1
* clang-formatSergiusz Bazanski2018-07-241-14/+21
* ice40: A slightly nicer way to do this.Sergiusz Bazanski2018-07-241-46/+31
* ice40: Refactor PLL/LOCK LUT splicing out into Arch::Sergiusz Bazanski2018-07-241-0/+1
* ice40: Implement emitting PLLsSergiusz Bazanski2018-07-241-14/+104
* clangformatDavid Shah2018-07-231-2/+3
* Move to new API and remove deprecatedMiodrag Milanovic2018-07-221-36/+38
* Rename getWireBelPin to getBelPinWireClifford Wolf2018-07-221-3/+3
* Added driver and users for netsMiodrag Milanovic2018-07-211-0/+8
* Map ports to netsMiodrag Milanovic2018-07-211-0/+14
* create io cells out of ascMiodrag Milanovic2018-07-211-0/+27
* add cells that are in default state or no configurationMiodrag Milanovic2018-07-211-0/+40
* Add used cells and attach them to belsMiodrag Milanovic2018-07-211-0/+39
* Assign proper pipsMiodrag Milanovic2018-07-211-9/+27
* add only missing netMiodrag Milanovic2018-07-211-3/+6
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