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* Use hashlib for core netlist structuresgatecat2021-06-025-12/+14
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Add hash() member functionsgatecat2021-06-021-0/+5
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* interchange: Add LIFCL-40 EVN testsgatecat2021-06-0110-1/+82
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* interchange: Add macro parameter mappinggatecat2021-05-212-3/+53
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* interchange: Don't error out on missing cell portsgatecat2021-05-212-2/+3
| | | | | | | This is required for LUTRAM support, as the upper address bits of RAMD64E etc are missing for shallower primitives. Signed-off-by: gatecat <gatecat@ds0.me>
* interchange: Add LUTRAM testgatecat2021-05-216-0/+169
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* interchange: Preliminary implementation of macro expansiongatecat2021-05-213-0/+116
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* interchange: Add macro param map rules to chipdbgatecat2021-05-211-0/+24
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* interchange: Add macro data to chipdbgatecat2021-05-211-1/+51
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* interchange: phys: add site instance idstr for pseudo tile PIPsAlessandro Comodi2021-05-191-0/+19
| | | | Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
* Run clangformatgatecat2021-05-162-5/+7
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* interchange: pseudo pips: fix illegal tile pseudo PIPsAlessandro Comodi2021-05-143-21/+62
| | | | Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
* interchange: site router: add valid pips list to check during routingAlessandro Comodi2021-05-133-11/+59
| | | | Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
* interchange: arch: do not allow site pips within sitesAlessandro Comodi2021-05-121-6/+0
| | | | | | | | | | | | During general routing, the only site pips that can be allowed are those which connect a site wire to the routing interface. This might be too restrictive when dealing with architectures that require more than one site PIPs to route from a driver within a site to the routing interface (which is something that should be allowed in the interchange). Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
* interchange: Fix bounding box computationgatecat2021-05-111-2/+2
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* interchange: site router: fix log messagesAlessandro Comodi2021-05-101-3/+3
| | | | Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
* interchange: site router: fix illegal site thru pathsAlessandro Comodi2021-05-102-0/+23
| | | | Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
* interchange: Adding a basic global buffer placergatecat2021-05-073-32/+132
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* interchange: Initial global routing implementationgatecat2021-05-073-0/+222
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* interchange: Add more global cell infogatecat2021-05-071-1/+14
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Add stub cluster API impl for remaining archesgatecat2021-05-062-0/+15
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* interchange/nexus: Add counter examplegatecat2021-04-308-3/+61
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* interchange: Implement getWireTypegatecat2021-04-301-1/+18
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* interchange: Add wire types to chipdbgatecat2021-04-301-1/+17
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Merge pull request #683 from antmicro/interchange-allow-loc-keywordgatecat2021-04-201-2/+4
|\ | | | | interchange: allow LOC keyword in XDC files
| * interchange: allow LOC keyword in XDC filesJan Kowalewski2021-04-201-2/+4
| | | | | | | | Signed-off-by: Jan Kowalewski <jkowalewski@antmicro.com>
* | interchange: Handle disconnected/missing cell pinsgatecat2021-04-193-6/+56
| | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
* | interchange: Add default cell connections to chipdbgatecat2021-04-191-1/+24
| | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
* | Add Python bindings for placement testsgatecat2021-04-151-0/+5
| | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
* | Merge pull request #678 from acomodi/initial-fasm-generationgatecat2021-04-1420-70/+135
|\ \ | | | | | | interchange: add FASM generation target and clean-up tests
| * | interchange: add FASM generation target and clean-up testsAlessandro Comodi2021-04-1420-70/+135
| |/ | | | | | | Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
* / Hash table refactoringgatecat2021-04-146-10/+11
|/ | | | Signed-off-by: gatecat <gatecat@ds0.me>
* interchange: Allow pseudo-cells with no input pinsgatecat2021-04-131-14/+35
| | | | | | | These are used for the LUT-as-GND-driver pseudo-pips in the Nexus arch, which will probably be required for UltraScale too. Signed-off-by: gatecat <gatecat@ds0.me>
* clangformatgatecat2021-04-128-133/+134
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* interchange: Disambiguate cell and bel pins when creating Vcc tiesgatecat2021-04-091-6/+10
| | | | | | | | | | | | The pins created for tieing to Vcc were being named after the bel pin, relying on the fact that Xilinx names cell and bel pins differently for LUTs. This isn't true for Nexus devices which uses the same names for both, and was causing a failure as a result. This uses a "PHYS_" prefix that's highly unlikely to appear in a cell pin name to disambiguate. Signed-off-by: gatecat <gatecat@ds0.me>
* [interchange] Provide estimateDelay when USE_LOOKAHEAD is not defined.Keith Rothman2021-04-061-1/+16
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* [interchange] Remove requirement to have wire_lut.Keith Rothman2021-04-063-6/+7
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* [interchange] Fix invalid use of local variables due to refactoring.Keith Rothman2021-04-063-6/+7
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* [interchange] Prevent site router from generating incorrect LUTs.Keith Rothman2021-04-063-42/+102
| | | | | | | | | The previous logic tied LUT input pins to VCC if a wire was unplacable. This missed a case where the net was present to the input of the LUT, but a wire was still not legal. This case is now prevented by tying the output of the LUT to an unused net. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* [interchange] Scale edge cost of pseudo pips.Keith Rothman2021-04-062-5/+12
| | | | | | | Previous pseudo pips were the same cost as regular pips, but this is definitely too fast, and meant that the router was prefering them. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* [interchange] Fix missing inline methods in site_arch.impl.hKeith Rothman2021-04-062-8/+9
| | | | | | | getBelPinWire and getBelPinType are marked as always inline, but were not defined in a header. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* [interchange] Disallow site edges during general routing.Keith Rothman2021-04-062-5/+23
| | | | | | | This prevents the general router from routing through sites, which is not legal in FPGA interchange. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* [interchange] Add crude pseudo pip model.Keith Rothman2021-04-066-7/+717
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Merge pull request #661 from litghost/document_site_routergatecat2021-04-061-10/+58
|\ | | | | [interchange] Add some documentation for the site router.
| * [interchange] Add some documentation for the site router.Keith Rothman2021-04-051-10/+58
| | | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* | Merge pull request #657 from acomodi/interchange-counter-multi-boardgatecat2021-04-065-23/+25
|\ \ | |/ |/| interchange: counter: testing on multiple boards
| * interchange: counter: testing on multiple boardsAlessandro Comodi2021-04-015-23/+25
| | | | | | | | Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
* | [interchange] Update to v6 of FPGA interchange chipdb.Keith Rothman2021-04-013-2/+12
|/ | | | | | | Changes: - Adds LUT output pin to LutBelPOD. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Merge pull request #646 from YosysHQ/gatecat/nexus-cmakegatecat2021-03-3113-126/+368
|\ | | | | fpga_interchange: Add CMake support for Nexus/prjoxide
| * interchange: Fix nexus cmake review commentsgatecat2021-03-313-9/+4
| | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
generated by cgit v1.2.3 (git 2.25.1) at 2025-02-21 07:49:45 +0000