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author | gatecat <gatecat@ds0.me> | 2021-06-01 16:51:18 +0100 |
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committer | gatecat <gatecat@ds0.me> | 2021-06-02 14:27:56 +0100 |
commit | 579b98c5963c2b86d191d481a2147a663a8196dd (patch) | |
tree | a37baaeac305fbb9d3f7db98ccda8a1708ac234c /fpga_interchange | |
parent | ff72454f8391ab4785fa8314f3efbbea96c30422 (diff) | |
download | nextpnr-579b98c5963c2b86d191d481a2147a663a8196dd.tar.gz nextpnr-579b98c5963c2b86d191d481a2147a663a8196dd.tar.bz2 nextpnr-579b98c5963c2b86d191d481a2147a663a8196dd.zip |
Use hashlib for core netlist structures
Signed-off-by: gatecat <gatecat@ds0.me>
Diffstat (limited to 'fpga_interchange')
-rw-r--r-- | fpga_interchange/arch.cc | 4 | ||||
-rw-r--r-- | fpga_interchange/arch_pybindings.cc | 8 | ||||
-rw-r--r-- | fpga_interchange/archdefs.h | 2 | ||||
-rw-r--r-- | fpga_interchange/globals.cc | 8 | ||||
-rw-r--r-- | fpga_interchange/macros.cc | 4 |
5 files changed, 14 insertions, 12 deletions
diff --git a/fpga_interchange/arch.cc b/fpga_interchange/arch.cc index 71c68e66..663587fd 100644 --- a/fpga_interchange/arch.cc +++ b/fpga_interchange/arch.cc @@ -2047,8 +2047,8 @@ void Arch::pack_default_conns() std::vector<IdString> dead_nets; - for (auto cell : sorted(ctx->cells)) { - CellInfo *ci = cell.second; + for (auto &cell : ctx->cells) { + CellInfo *ci = cell.second.get(); const DefaultCellConnsPOD *conns = get_default_conns(ci->type); if (conns == nullptr) continue; diff --git a/fpga_interchange/arch_pybindings.cc b/fpga_interchange/arch_pybindings.cc index 68619866..03b20841 100644 --- a/fpga_interchange/arch_pybindings.cc +++ b/fpga_interchange/arch_pybindings.cc @@ -49,10 +49,10 @@ void arch_wrap_python(py::module &m) fn_wrapper_1a_v<Context, decltype(&Context::explain_bel_status), &Context::explain_bel_status, conv_from_str<BelId>>::def_wrap(ctx_cls, "explain_bel_status"); - typedef std::unordered_map<IdString, std::unique_ptr<CellInfo>> CellMap; - typedef std::unordered_map<IdString, std::unique_ptr<NetInfo>> NetMap; - typedef std::unordered_map<IdString, IdString> AliasMap; - typedef std::unordered_map<IdString, HierarchicalCell> HierarchyMap; + typedef dict<IdString, std::unique_ptr<CellInfo>> CellMap; + typedef dict<IdString, std::unique_ptr<NetInfo>> NetMap; + typedef dict<IdString, IdString> AliasMap; + typedef dict<IdString, HierarchicalCell> HierarchyMap; auto belpin_cls = py::class_<ContextualWrapper<BelPin>>(m, "BelPin"); readonly_wrapper<BelPin, decltype(&BelPin::bel), &BelPin::bel, conv_to_str<BelId>>::def_wrap(belpin_cls, "bel"); diff --git a/fpga_interchange/archdefs.h b/fpga_interchange/archdefs.h index aa3f1e6e..ba4fe054 100644 --- a/fpga_interchange/archdefs.h +++ b/fpga_interchange/archdefs.h @@ -85,12 +85,14 @@ struct GroupId { bool operator==(const GroupId &other) const { return true; } bool operator!=(const GroupId &other) const { return false; } + unsigned int hash() const { return 0; } }; struct DecalId { bool operator==(const DecalId &other) const { return true; } bool operator!=(const DecalId &other) const { return false; } + unsigned int hash() const { return 0; } }; struct BelBucketId diff --git a/fpga_interchange/globals.cc b/fpga_interchange/globals.cc index 66d04f75..918b916e 100644 --- a/fpga_interchange/globals.cc +++ b/fpga_interchange/globals.cc @@ -160,8 +160,8 @@ void Arch::place_globals() // TODO: for more complex PLL type setups, we might want a toposort or iterative loop as the PLL must be placed // before the GBs it drives - for (auto cell : sorted(ctx->cells)) { - CellInfo *ci = cell.second; + for (auto &cell : ctx->cells) { + CellInfo *ci = cell.second.get(); const GlobalCellPOD *glb_cell = global_cell_info(ci->type); if (glb_cell == nullptr) continue; @@ -239,8 +239,8 @@ void Arch::route_globals() IdString gnd_net_name(chip_info->constants->gnd_net_name); IdString vcc_net_name(chip_info->constants->vcc_net_name); - for (auto cell : sorted(ctx->cells)) { - CellInfo *ci = cell.second; + for (auto &cell : ctx->cells) { + CellInfo *ci = cell.second.get(); const GlobalCellPOD *glb_cell = global_cell_info(ci->type); if (glb_cell == nullptr) continue; diff --git a/fpga_interchange/macros.cc b/fpga_interchange/macros.cc index eee35d9f..8339829f 100644 --- a/fpga_interchange/macros.cc +++ b/fpga_interchange/macros.cc @@ -53,8 +53,8 @@ void Arch::expand_macros() // Make up a list of cells, so we don't have modify-while-iterating issues Context *ctx = getCtx(); std::vector<CellInfo *> cells; - for (auto cell : sorted(ctx->cells)) - cells.push_back(cell.second); + for (auto &cell : ctx->cells) + cells.push_back(cell.second.get()); std::vector<CellInfo *> next_cells; |