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* interchange: Disambiguate cell and bel pins when creating Vcc tiesgatecat2021-04-091-6/+10
* [interchange] Provide estimateDelay when USE_LOOKAHEAD is not defined.Keith Rothman2021-04-061-1/+16
* [interchange] Remove requirement to have wire_lut.Keith Rothman2021-04-063-6/+7
* [interchange] Fix invalid use of local variables due to refactoring.Keith Rothman2021-04-063-6/+7
* [interchange] Prevent site router from generating incorrect LUTs.Keith Rothman2021-04-063-42/+102
* [interchange] Scale edge cost of pseudo pips.Keith Rothman2021-04-062-5/+12
* [interchange] Fix missing inline methods in site_arch.impl.hKeith Rothman2021-04-062-8/+9
* [interchange] Disallow site edges during general routing.Keith Rothman2021-04-062-5/+23
* [interchange] Add crude pseudo pip model.Keith Rothman2021-04-066-7/+717
* Merge pull request #661 from litghost/document_site_routergatecat2021-04-061-10/+58
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| * [interchange] Add some documentation for the site router.Keith Rothman2021-04-051-10/+58
* | Merge pull request #657 from acomodi/interchange-counter-multi-boardgatecat2021-04-065-23/+25
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| * interchange: counter: testing on multiple boardsAlessandro Comodi2021-04-015-23/+25
* | [interchange] Update to v6 of FPGA interchange chipdb.Keith Rothman2021-04-013-2/+12
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* Merge pull request #646 from YosysHQ/gatecat/nexus-cmakegatecat2021-03-3113-126/+368
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| * interchange: Fix nexus cmake review commentsgatecat2021-03-313-9/+4
| * interchange: Split xc7 and nexus chipdb cmakegatecat2021-03-303-243/+245
| * interchange: Add Nexus LUT testgatecat2021-03-307-19/+139
| * interchange: Add Nexus to CIgatecat2021-03-303-1/+11
| * interchange: Add CMake support for Nexus/prjoxidegatecat2021-03-303-0/+115
* | Fix bug where DedicateInterconnect incorrectly allows some placement.Keith Rothman2021-03-302-10/+23
* | [interchange] Fix site pip check for drivers.Keith Rothman2021-03-301-7/+22
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* interchange: Fix illegal placementsgatecat2021-03-301-6/+5
* Merge pull request #645 from litghost/add_counter_and_ramgatecat2021-03-2922-335/+1218
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| * Update README with latest develpment progress.Keith Rothman2021-03-252-146/+39
| * interchange: Fix bug in site router where a bad solution isn't remove.Keith Rothman2021-03-251-3/+7
| * Implement debugging tools for site router.Keith Rothman2021-03-257-23/+166
| * Add some FIXME's around VCC assumption in LUT logic.Keith Rothman2021-03-251-0/+17
| * Add targets to generate YAML outputs for DeviceResource files.Keith Rothman2021-03-251-0/+22
| * Re-work LUT mapping logic to only put VCC pins when required.Keith Rothman2021-03-255-104/+174
| * Fixup some of the re-mapping logic.Keith Rothman2021-03-252-27/+75
| * Add initial handling of local site inverters and constant signals.Keith Rothman2021-03-257-58/+457
| * [FPGA interchange] Small fix to get_net_type.Keith Rothman2021-03-252-9/+14
| * Enable counter tests and add RAM tests.Keith Rothman2021-03-256-2/+284
* | interchange: add archcheck tests to all-device-test targetAlessandro Comodi2021-03-261-1/+6
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* gh-actions: interchange: multiple jobs, one for each deviceAlessandro Comodi2021-03-242-1/+5
* interchange: examples: remove unused makefilesAlessandro Comodi2021-03-242-99/+0
* interchange: devices: bel_bucket_seeds -> device_configAlessandro Comodi2021-03-233-3/+3
* interchange: added boards and group testing across multiple boardsAlessandro Comodi2021-03-2310-45/+155
* fpga_interchange: add test data for new architecturesAlessandro Comodi2021-03-233-0/+108
* fpga_interchange: use higher java heap spaceAlessandro Comodi2021-03-233-3/+4
* fpga_interchange: add more devicesAlessandro Comodi2021-03-238-3/+91
* Merge pull request #644 from litghost/add_global_buffersgatecat2021-03-234-10/+29
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| * [FPGA interchange] Add support for global buffers from chipdb.Keith Rothman2021-03-234-10/+29
* | Merge pull request #643 from litghost/id_constantsgatecat2021-03-232-4/+27
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| * | [FPGA interchange] Convert some string constants to IdString.Keith Rothman2021-03-232-4/+27
* | | Merge pull request #640 from litghost/inversion_logicgatecat2021-03-237-8/+131
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| * | Initial version of inverter logic.Keith Rothman2021-03-237-8/+131
* | | Merge pull request #639 from litghost/parameter_iterationgatecat2021-03-235-42/+315
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| * Update FPGA interchange chipdb to v4 with inverter data.Keith Rothman2021-03-231-1/+22