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| author | Keith Rothman <537074+litghost@users.noreply.github.com> | 2021-03-22 17:38:15 -0700 |
|---|---|---|
| committer | Keith Rothman <537074+litghost@users.noreply.github.com> | 2021-03-23 09:01:45 -0700 |
| commit | ae71206e1f9522542b919b0dd5b3e634a680dc03 (patch) | |
| tree | 8ad86eb300731e22d884d590d4b2d58802dc7109 /fpga_interchange | |
| parent | 8a50b02b9bbaf292fb6294eda5df162f3295f149 (diff) | |
| download | nextpnr-ae71206e1f9522542b919b0dd5b3e634a680dc03.tar.gz nextpnr-ae71206e1f9522542b919b0dd5b3e634a680dc03.tar.bz2 nextpnr-ae71206e1f9522542b919b0dd5b3e634a680dc03.zip | |
Update FPGA interchange chipdb to v4 with inverter data.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
Diffstat (limited to 'fpga_interchange')
| -rw-r--r-- | fpga_interchange/chipdb.h | 23 |
1 files changed, 22 insertions, 1 deletions
diff --git a/fpga_interchange/chipdb.h b/fpga_interchange/chipdb.h index 78c56471..5c9a9c52 100644 --- a/fpga_interchange/chipdb.h +++ b/fpga_interchange/chipdb.h @@ -34,7 +34,7 @@ NEXTPNR_NAMESPACE_BEGIN * kExpectedChipInfoVersion */ -static constexpr int32_t kExpectedChipInfoVersion = 3; +static constexpr int32_t kExpectedChipInfoVersion = 4; // Flattened site indexing. // @@ -71,6 +71,15 @@ NPNR_PACKED_STRUCT(struct BelInfoPOD { int8_t lut_element; RelPtr<int32_t> pin_map; // Index into CellMapPOD::cell_bel_map + + // If this BEL is a site routing BEL with inverting pins, these values + // will be [0, num_bel_wires). If this BEL is either not a site routing + // BEL or this site routing has no inversion capabilities, then these will + // both be -1. + int8_t non_inverting_pin; + int8_t inverting_pin; + + int16_t padding; }); enum BELCategory @@ -261,6 +270,10 @@ NPNR_PACKED_STRUCT(struct ConstantsPOD { // Name to use for the global VCC constant net int32_t vcc_net_name; // constid + + // If a choice is available, which constant net should be used? + // Can be ''/0 if either constant net are equivilent. + int32_t best_constant_net; // constid }); NPNR_PACKED_STRUCT(struct ChipInfoPOD { @@ -315,6 +328,14 @@ inline const SiteInstInfoPOD &site_inst_info(const ChipInfoPOD *chip_info, int32 return chip_info->sites[chip_info->tiles[tile].sites[site]]; } +enum SyntheticType +{ + NOT_SYNTH = 0, + SYNTH_SIGNAL = 1, + SYNTH_GND = 2, + SYNTH_VCC = 3, +}; + NEXTPNR_NAMESPACE_END #endif /* CHIPDB_H */ |