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* Fixing old emails and names in copyrightsgatecat2021-06-127-9/+9
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* interchange: clusters: always get cell bel map and add assertsAlessandro Comodi2021-06-111-23/+13
| | | | Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
* interchange: run clang formatterAlessandro Comodi2021-06-112-22/+18
| | | | Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
* interchange: clusters: adjust commentsAlessandro Comodi2021-06-112-11/+16
| | | | Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
* interchange: increase chipinfo versionAlessandro Comodi2021-06-111-1/+1
| | | | Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
* interchange: tests: counter: emit carries for xc7Alessandro Comodi2021-06-112-4/+6
| | | | Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
* interchange: add support for generating BEL clustersAlessandro Comodi2021-06-119-24/+713
| | | | | | | | Clustering greatly helps the placer to identify and pack together specific cells at the same site (e.g. LUT+FF), or cells that are chained through dedicated interconnections (e.g. CARRY CHAINS) Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
* fpga_interchange: Add site router testsTomasz Michalak2021-06-111-0/+3
| | | | Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
* Remove redundant code after hashlib movegatecat2021-06-021-65/+0
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Use hashlib in most remaining codegatecat2021-06-021-2/+2
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Using hashlib in archesgatecat2021-06-0225-326/+176
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Use hashlib for core netlist structuresgatecat2021-06-025-12/+14
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Add hash() member functionsgatecat2021-06-021-0/+5
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* interchange: Add LIFCL-40 EVN testsgatecat2021-06-0110-1/+82
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* interchange: Add macro parameter mappinggatecat2021-05-212-3/+53
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* interchange: Don't error out on missing cell portsgatecat2021-05-212-2/+3
| | | | | | | This is required for LUTRAM support, as the upper address bits of RAMD64E etc are missing for shallower primitives. Signed-off-by: gatecat <gatecat@ds0.me>
* interchange: Add LUTRAM testgatecat2021-05-216-0/+169
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* interchange: Preliminary implementation of macro expansiongatecat2021-05-213-0/+116
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* interchange: Add macro param map rules to chipdbgatecat2021-05-211-0/+24
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* interchange: Add macro data to chipdbgatecat2021-05-211-1/+51
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* interchange: phys: add site instance idstr for pseudo tile PIPsAlessandro Comodi2021-05-191-0/+19
| | | | Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
* Run clangformatgatecat2021-05-162-5/+7
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* interchange: pseudo pips: fix illegal tile pseudo PIPsAlessandro Comodi2021-05-143-21/+62
| | | | Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
* interchange: site router: add valid pips list to check during routingAlessandro Comodi2021-05-133-11/+59
| | | | Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
* interchange: arch: do not allow site pips within sitesAlessandro Comodi2021-05-121-6/+0
| | | | | | | | | | | | During general routing, the only site pips that can be allowed are those which connect a site wire to the routing interface. This might be too restrictive when dealing with architectures that require more than one site PIPs to route from a driver within a site to the routing interface (which is something that should be allowed in the interchange). Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
* interchange: Fix bounding box computationgatecat2021-05-111-2/+2
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* interchange: site router: fix log messagesAlessandro Comodi2021-05-101-3/+3
| | | | Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
* interchange: site router: fix illegal site thru pathsAlessandro Comodi2021-05-102-0/+23
| | | | Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
* interchange: Adding a basic global buffer placergatecat2021-05-073-32/+132
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* interchange: Initial global routing implementationgatecat2021-05-073-0/+222
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* interchange: Add more global cell infogatecat2021-05-071-1/+14
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Add stub cluster API impl for remaining archesgatecat2021-05-062-0/+15
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* interchange/nexus: Add counter examplegatecat2021-04-308-3/+61
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* interchange: Implement getWireTypegatecat2021-04-301-1/+18
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* interchange: Add wire types to chipdbgatecat2021-04-301-1/+17
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Merge pull request #683 from antmicro/interchange-allow-loc-keywordgatecat2021-04-201-2/+4
|\ | | | | interchange: allow LOC keyword in XDC files
| * interchange: allow LOC keyword in XDC filesJan Kowalewski2021-04-201-2/+4
| | | | | | | | Signed-off-by: Jan Kowalewski <jkowalewski@antmicro.com>
* | interchange: Handle disconnected/missing cell pinsgatecat2021-04-193-6/+56
| | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
* | interchange: Add default cell connections to chipdbgatecat2021-04-191-1/+24
| | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
* | Add Python bindings for placement testsgatecat2021-04-151-0/+5
| | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
* | Merge pull request #678 from acomodi/initial-fasm-generationgatecat2021-04-1420-70/+135
|\ \ | | | | | | interchange: add FASM generation target and clean-up tests
| * | interchange: add FASM generation target and clean-up testsAlessandro Comodi2021-04-1420-70/+135
| |/ | | | | | | Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
* / Hash table refactoringgatecat2021-04-146-10/+11
|/ | | | Signed-off-by: gatecat <gatecat@ds0.me>
* interchange: Allow pseudo-cells with no input pinsgatecat2021-04-131-14/+35
| | | | | | | These are used for the LUT-as-GND-driver pseudo-pips in the Nexus arch, which will probably be required for UltraScale too. Signed-off-by: gatecat <gatecat@ds0.me>
* clangformatgatecat2021-04-128-133/+134
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* interchange: Disambiguate cell and bel pins when creating Vcc tiesgatecat2021-04-091-6/+10
| | | | | | | | | | | | The pins created for tieing to Vcc were being named after the bel pin, relying on the fact that Xilinx names cell and bel pins differently for LUTs. This isn't true for Nexus devices which uses the same names for both, and was causing a failure as a result. This uses a "PHYS_" prefix that's highly unlikely to appear in a cell pin name to disambiguate. Signed-off-by: gatecat <gatecat@ds0.me>
* [interchange] Provide estimateDelay when USE_LOOKAHEAD is not defined.Keith Rothman2021-04-061-1/+16
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* [interchange] Remove requirement to have wire_lut.Keith Rothman2021-04-063-6/+7
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* [interchange] Fix invalid use of local variables due to refactoring.Keith Rothman2021-04-063-6/+7
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* [interchange] Prevent site router from generating incorrect LUTs.Keith Rothman2021-04-063-42/+102
| | | | | | | | | The previous logic tied LUT input pins to VCC if a wire was unplacable. This missed a case where the net was present to the input of the LUT, but a wire was still not legal. This case is now prevented by tying the output of the LUT to an unused net. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-08-28 06:55:28 +0000