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authorDavid Shah <davey1576@gmail.com>2019-04-19 17:40:55 +0100
committerGitHub <noreply@github.com>2019-04-19 17:40:55 +0100
commit5344bc3b65f4e06f983db781e9a82d30b3f1512b (patch)
tree5f794074ccc963a9dbf756558e34a8eba0d5fa26 /generic/examples/simple_timing.py
parent0be844e6a8d0a36a50815ec5331fd7480dd20db6 (diff)
parent87a24460813b9f52189323352554a1c352836ee2 (diff)
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Merge pull request #261 from YosysHQ/pygeneric
Python API for generic architecture
Diffstat (limited to 'generic/examples/simple_timing.py')
-rw-r--r--generic/examples/simple_timing.py15
1 files changed, 15 insertions, 0 deletions
diff --git a/generic/examples/simple_timing.py b/generic/examples/simple_timing.py
new file mode 100644
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+++ b/generic/examples/simple_timing.py
@@ -0,0 +1,15 @@
+for cname, cell in ctx.cells:
+ if cell.type != "GENERIC_SLICE":
+ continue
+ if cname in ("$PACKER_GND", "$PACKER_VCC"):
+ continue
+ K = int(cell.params["K"])
+ if cell.params["FF_USED"] == "1":
+ ctx.addCellTimingClock(cell=cname, port="CLK")
+ for i in range(K):
+ ctx.addCellTimingSetupHold(cell=cname, port="I[%d]" % i, clock="CLK",
+ setup=ctx.getDelayFromNS(0.2), hold=ctx.getDelayFromNS(0))
+ ctx.addCellTimingClockToOut(cell=cname, port="Q", clock="CLK", clktoq=ctx.getDelayFromNS(0.2))
+ else:
+ for i in range(K):
+ ctx.addCellTimingDelay(cell=cname, fromPort="I[%d]" % i, toPort="Q", delay=ctx.getDelayFromNS(0.2)) \ No newline at end of file