From f0cd51e6bc58f3dfd1185fd53ad970ba634359f2 Mon Sep 17 00:00:00 2001 From: David Shah Date: Thu, 4 Apr 2019 16:30:47 +0100 Subject: generic: Cell timing support Signed-off-by: David Shah --- generic/examples/simple_timing.py | 15 +++++++++++++++ 1 file changed, 15 insertions(+) create mode 100644 generic/examples/simple_timing.py (limited to 'generic/examples/simple_timing.py') diff --git a/generic/examples/simple_timing.py b/generic/examples/simple_timing.py new file mode 100644 index 00000000..a955c8d7 --- /dev/null +++ b/generic/examples/simple_timing.py @@ -0,0 +1,15 @@ +for cname, cell in ctx.cells: + if cell.type != "GENERIC_SLICE": + continue + if cname in ("$PACKER_GND", "$PACKER_VCC"): + continue + K = int(cell.params["K"]) + if cell.params["FF_USED"] == "1": + ctx.addCellTimingClock(cell=cname, port="CLK") + for i in range(K): + ctx.addCellTimingSetupHold(cell=cname, port="I[%d]" % i, clock="CLK", + setup=ctx.getDelayFromNS(0.2), hold=ctx.getDelayFromNS(0)) + ctx.addCellTimingClockToOut(cell=cname, port="Q", clock="CLK", clktoq=ctx.getDelayFromNS(0.2)) + else: + for i in range(K): + ctx.addCellTimingDelay(cell=cname, fromPort="I[%d]" % i, toPort="Q", delay=ctx.getDelayFromNS(0.2)) \ No newline at end of file -- cgit v1.2.3