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| author | YRabbit <rabbit@yrabbit.cyou> | 2022-07-10 08:05:25 +1000 |
|---|---|---|
| committer | YRabbit <rabbit@yrabbit.cyou> | 2022-07-10 08:05:25 +1000 |
| commit | ecddac7b18526940db529389b7efdae299b7dd12 (patch) | |
| tree | fb27cb7b7d8a3a79d7d1b14049396a9cf2596dd6 /fpga_interchange | |
| parent | 1ebfe67daf2ec3e1e64150f09ab4c194f41d1d9d (diff) | |
| parent | 664cec54b92844745e21a4e86dcf8e3cca09d781 (diff) | |
| download | nextpnr-ecddac7b18526940db529389b7efdae299b7dd12.tar.gz nextpnr-ecddac7b18526940db529389b7efdae299b7dd12.tar.bz2 nextpnr-ecddac7b18526940db529389b7efdae299b7dd12.zip | |
Merge branch 'master' into clock-wip
Diffstat (limited to 'fpga_interchange')
| -rw-r--r-- | fpga_interchange/arch.h | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/fpga_interchange/arch.h b/fpga_interchange/arch.h index 789b188e..aeb5578f 100644 --- a/fpga_interchange/arch.h +++ b/fpga_interchange/arch.h @@ -748,11 +748,11 @@ struct Arch : ArchAPI<ArchRanges> // Get the delay through a cell from one port to another, returning false // if no path exists. This only considers combinational delays, as required by the Arch API - bool getCellDelay(const CellInfo *cell, IdString fromPort, IdString toPort, DelayQuad &delay) const final; + bool getCellDelay(const CellInfo *cell, IdString fromPort, IdString toPort, DelayQuad &delay) const; // Get the port class, also setting clockInfoCount to the number of TimingClockingInfos associated with a port - TimingPortClass getPortTimingClass(const CellInfo *cell, IdString port, int &clockInfoCount) const final; + TimingPortClass getPortTimingClass(const CellInfo *cell, IdString port, int &clockInfoCount) const; // Get the TimingClockingInfo of a port - TimingClockingInfo getPortClockingInfo(const CellInfo *cell, IdString port, int index) const final; + TimingClockingInfo getPortClockingInfo(const CellInfo *cell, IdString port, int index) const; // ------------------------------------------------- |