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| author | myrtle <gatecat@ds0.me> | 2022-07-08 15:03:07 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2022-07-08 15:03:07 +0200 |
| commit | 664cec54b92844745e21a4e86dcf8e3cca09d781 (patch) | |
| tree | 004f2b14ed5a3b0584c4998d9f0a5598cc52ab28 /fpga_interchange | |
| parent | 86396c41d64d2583ec1dffca4298e83d927f0762 (diff) | |
| parent | 09e388f453d9cf998391495349c88e5478b62e34 (diff) | |
| download | nextpnr-664cec54b92844745e21a4e86dcf8e3cca09d781.tar.gz nextpnr-664cec54b92844745e21a4e86dcf8e3cca09d781.tar.bz2 nextpnr-664cec54b92844745e21a4e86dcf8e3cca09d781.zip | |
Merge pull request #999 from YosysHQ/gatecat/pseudocell-api
netlist: Add PseudoCell API
Diffstat (limited to 'fpga_interchange')
| -rw-r--r-- | fpga_interchange/arch.h | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/fpga_interchange/arch.h b/fpga_interchange/arch.h index 789b188e..aeb5578f 100644 --- a/fpga_interchange/arch.h +++ b/fpga_interchange/arch.h @@ -748,11 +748,11 @@ struct Arch : ArchAPI<ArchRanges> // Get the delay through a cell from one port to another, returning false // if no path exists. This only considers combinational delays, as required by the Arch API - bool getCellDelay(const CellInfo *cell, IdString fromPort, IdString toPort, DelayQuad &delay) const final; + bool getCellDelay(const CellInfo *cell, IdString fromPort, IdString toPort, DelayQuad &delay) const; // Get the port class, also setting clockInfoCount to the number of TimingClockingInfos associated with a port - TimingPortClass getPortTimingClass(const CellInfo *cell, IdString port, int &clockInfoCount) const final; + TimingPortClass getPortTimingClass(const CellInfo *cell, IdString port, int &clockInfoCount) const; // Get the TimingClockingInfo of a port - TimingClockingInfo getPortClockingInfo(const CellInfo *cell, IdString port, int index) const final; + TimingClockingInfo getPortClockingInfo(const CellInfo *cell, IdString port, int index) const; // ------------------------------------------------- |