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| author | gatecat <gatecat@ds0.me> | 2021-06-01 16:51:18 +0100 |
|---|---|---|
| committer | gatecat <gatecat@ds0.me> | 2021-06-02 14:27:56 +0100 |
| commit | 579b98c5963c2b86d191d481a2147a663a8196dd (patch) | |
| tree | a37baaeac305fbb9d3f7db98ccda8a1708ac234c /fpga_interchange/globals.cc | |
| parent | ff72454f8391ab4785fa8314f3efbbea96c30422 (diff) | |
| download | nextpnr-579b98c5963c2b86d191d481a2147a663a8196dd.tar.gz nextpnr-579b98c5963c2b86d191d481a2147a663a8196dd.tar.bz2 nextpnr-579b98c5963c2b86d191d481a2147a663a8196dd.zip | |
Use hashlib for core netlist structures
Signed-off-by: gatecat <gatecat@ds0.me>
Diffstat (limited to 'fpga_interchange/globals.cc')
| -rw-r--r-- | fpga_interchange/globals.cc | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/fpga_interchange/globals.cc b/fpga_interchange/globals.cc index 66d04f75..918b916e 100644 --- a/fpga_interchange/globals.cc +++ b/fpga_interchange/globals.cc @@ -160,8 +160,8 @@ void Arch::place_globals() // TODO: for more complex PLL type setups, we might want a toposort or iterative loop as the PLL must be placed // before the GBs it drives - for (auto cell : sorted(ctx->cells)) { - CellInfo *ci = cell.second; + for (auto &cell : ctx->cells) { + CellInfo *ci = cell.second.get(); const GlobalCellPOD *glb_cell = global_cell_info(ci->type); if (glb_cell == nullptr) continue; @@ -239,8 +239,8 @@ void Arch::route_globals() IdString gnd_net_name(chip_info->constants->gnd_net_name); IdString vcc_net_name(chip_info->constants->vcc_net_name); - for (auto cell : sorted(ctx->cells)) { - CellInfo *ci = cell.second; + for (auto &cell : ctx->cells) { + CellInfo *ci = cell.second.get(); const GlobalCellPOD *glb_cell = global_cell_info(ci->type); if (glb_cell == nullptr) continue; |