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| author | David Shah <davey1576@gmail.com> | 2017-11-19 19:32:22 +0000 |
|---|---|---|
| committer | David Shah <davey1576@gmail.com> | 2017-11-19 19:32:22 +0000 |
| commit | 8c0fe225ca925caed45f721303b55386b8944e62 (patch) | |
| tree | 55c28ee318f5e08641ccac6b0fec01de68e8ae50 | |
| parent | 548aa14997d4517988deaa35f9b9eb47a1b450a2 (diff) | |
| download | icestorm-8c0fe225ca925caed45f721303b55386b8944e62.tar.gz icestorm-8c0fe225ca925caed45f721303b55386b8944e62.tar.bz2 icestorm-8c0fe225ca925caed45f721303b55386b8944e62.zip | |
Add UltraPlus info to docs
| -rw-r--r-- | docs/index.html | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/docs/index.html b/docs/index.html index a18dfe2..6b3ff5e 100644 --- a/docs/index.html +++ b/docs/index.html @@ -101,6 +101,11 @@ Here is a list of currently supported parts and the corresponding options for ar </table> <p> + Experimental support is also included for one iCE40 UltraPlus device, the iCE40-UP5K-SG48, including support for some of + the new UltraPlus features such as DSPs, SPRAM and internal oscillators. +</p> + +<p> Current work focuses on further improving our timing analysis flow. </p> @@ -309,6 +314,8 @@ The FPGA fabric is divided into tiles. There are IO, RAM and LOGIC tiles. <li><a href="format.html">The Bitstream File Format</a></li> <li><a href="bitdocs-1k/">The iCE40 HX1K Bit Docs</a></li> <li><a href="bitdocs-8k/">The iCE40 HX8K Bit Docs</a></li> +<li><a href="ultraplus.html">Notes on UltraPlus features</a></li> + </ul> <p> |