From 8c0fe225ca925caed45f721303b55386b8944e62 Mon Sep 17 00:00:00 2001
From: David Shah <davey1576@gmail.com>
Date: Sun, 19 Nov 2017 19:32:22 +0000
Subject: Add UltraPlus info to docs

---
 docs/index.html | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/docs/index.html b/docs/index.html
index a18dfe2..6b3ff5e 100644
--- a/docs/index.html
+++ b/docs/index.html
@@ -100,6 +100,11 @@ Here is a list of currently supported parts and the corresponding options for ar
 <tr><td>iCE40-HX8K-CT256</td><td>256-ball caBGA (14 x 14 mm)</td><td>0.80 mm</td><td>206</td><td>-d 8k -P ct256</td><td>-d hx8k</td></tr>
 </table>
 
+<p>
+	Experimental support is also included for one iCE40 UltraPlus device, the iCE40-UP5K-SG48, including support for some of
+	the new UltraPlus features such as DSPs, SPRAM and internal oscillators.
+</p>
+
 <p>
 Current work focuses on further improving our timing analysis flow.
 </p>
@@ -309,6 +314,8 @@ The FPGA fabric is divided into tiles. There are IO, RAM and LOGIC tiles.
 <li><a href="format.html">The Bitstream File Format</a></li>
 <li><a href="bitdocs-1k/">The iCE40 HX1K Bit Docs</a></li>
 <li><a href="bitdocs-8k/">The iCE40 HX8K Bit Docs</a></li>
+<li><a href="ultraplus.html">Notes on UltraPlus features</a></li>
+
 </ul>
 
 <p>
-- 
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