testsuite/synth/dff02/dff08.vhdl


1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25

library ieee;
use ieee.std_logic_1164.all;

entity dff08 is
  port (q : out std_logic_vector(7 downto 0);
        d : std_logic_vector(7 downto 0);
        clk : std_logic;
        en : std_logic;
        rst : std_logic);
end dff08;

architecture behav of dff08 is
  signal p : std_logic_vector(7 downto 0);
begin
  process (clk, rst) is
  begin
    if en = '0' then
      null;
    elsif rst = '1' then
      q <= x"00";
    elsif rising_edge (clk) then
      q <= d;
    end if;
  end process;
end behav;