| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | synth-vhdl_eval: handle vector match, numeric_bit.to_unsigned | Tristan Gingold | 2022-05-31 | 2 | -7/+73 |
| * | vhdl: recognize numeric_bit.to_unsigned | Tristan Gingold | 2022-05-31 | 4 | -5/+57 |
| * | synth-vhdl_stmts: do not convert out variable on call | Tristan Gingold | 2022-05-31 | 1 | -3/+8 |
| * | synth-vhdl_stmts: export Synth_Subprogram_Back_Association | Tristan Gingold | 2022-05-31 | 2 | -7/+15 |
| * | synth-vhdl_static_proc: handle write_real | Tristan Gingold | 2022-05-31 | 1 | -0/+32 |
| * | synth-vhdl_eval: handle more operations (to_string, match) | Tristan Gingold | 2022-05-31 | 2 | -23/+229 |
| * | synth-vhdl_eval: handle more operators | Tristan Gingold | 2022-05-30 | 3 | -26/+402 |
| * | synth-vhdl_static_proc: add hook for std.env.finish | Tristan Gingold | 2022-05-30 | 2 | -0/+12 |
| * | synth-vhdl_oper: add hooks for bit edge | Tristan Gingold | 2022-05-30 | 2 | -0/+15 |
| * | vhdl-nodes: move maximum/minimum out of predefined operator range | Tristan Gingold | 2022-05-30 | 3 | -64/+67 |
| * | elab-vhdl_objtypes: bit and logic types also have a range | Tristan Gingold | 2022-05-30 | 2 | -6/+13 |
| * | synth-vhdl_eval: handle more operations | Tristan Gingold | 2022-05-29 | 5 | -23/+219 |
| * | synth-vhdl_eval: handle resolution_limit | Tristan Gingold | 2022-05-29 | 1 | -0/+3 |
| * | vhdl: recognize subprograms from std.env | Tristan Gingold | 2022-05-29 | 4 | -0/+98 |
| * | std_names: add names from std.env | Tristan Gingold | 2022-05-29 | 2 | -4/+13 |
| * | elab-debugger: export more subprograms | Tristan Gingold | 2022-05-29 | 1 | -0/+6 |
| * | ghdlsimul: use assertion level from command line | Tristan Gingold | 2022-05-29 | 1 | -0/+2 |
| * | synth-vhdl_stmts: export two procedures, adjust assertion message | Tristan Gingold | 2022-05-29 | 2 | -5/+10 |
| * | synth-vhdl_oper: add hook for falling edge, handle aliases. | Tristan Gingold | 2022-05-29 | 3 | -3/+13 |
| * | synth-vhdl_eval: handle more operations | Tristan Gingold | 2022-05-29 | 1 | -0/+30 |
| * | elab-vhdl_objtypes: add unshare with areapool | Tristan Gingold | 2022-05-29 | 2 | -0/+13 |
| * | synth: handle suspend state declaration and statement | Tristan Gingold | 2022-05-27 | 2 | -0/+16 |
| * | ghdlsimul: initial stop is after elaboration | Tristan Gingold | 2022-05-27 | 1 | -8/+1 |
| * | elab-debugger: add Debug_Time | Tristan Gingold | 2022-05-27 | 2 | -1/+16 |
| * | elab-vhdl_debug: handle records in disp_memtyp. | Tristan Gingold | 2022-05-27 | 2 | -4/+32 |
| * | elab-vhdl_objtypes: add Create_Memory_U32 (for states) | Tristan Gingold | 2022-05-27 | 2 | -3/+19 |
| * | utils_io: add put_addr (to display addresses) | Tristan Gingold | 2022-05-27 | 2 | -0/+24 |
| * | vhdl-canon: add Canon_Add_Suspend_State | Tristan Gingold | 2022-05-26 | 11 | -197/+508 |
| * | synth: move procedure call copyback values in context | Tristan Gingold | 2022-05-25 | 3 | -79/+82 |
| * | vhdl-annotations: annotate procedure call associations | Tristan Gingold | 2022-05-25 | 1 | -14/+47 |
| * | vhdl: move Is_Copyback_Parameter to vhdl-utils | Tristan Gingold | 2022-05-25 | 3 | -12/+16 |
| * | synth: add value_dyn_alias in elab-vhdl_values | Tristan Gingold | 2022-05-25 | 8 | -72/+203 |
| * | elab-vhdl_objtypes: use value_offsets for record elements offset. | Tristan Gingold | 2022-05-24 | 12 | -56/+52 |
| * | synth-vhdl_stmts: minor refactoring | Tristan Gingold | 2022-05-24 | 1 | -12/+23 |
| * | synth-vhdl_eval: handle element-element concatenation | Tristan Gingold | 2022-05-24 | 1 | -0/+18 |
| * | elab-vhdl_values-debug: slightly improve output | Tristan Gingold | 2022-05-24 | 1 | -2/+6 |
| * | synth-vhdl_stmts: rework synth_subprogram_association | Tristan Gingold | 2022-05-23 | 1 | -35/+35 |
| * | synth-vhdl_oper: add an hook for rising_edge | Tristan Gingold | 2022-05-23 | 3 | -4/+13 |
| * | elab-vhdl_objtypes: replace Is_Synth by Wkind | Tristan Gingold | 2022-05-22 | 3 | -23/+40 |
| * | synth: use same elements for unbounded arrays and vectors | Tristan Gingold | 2022-05-22 | 9 | -70/+36 |
| * | synth: also use one-dimensional unbounded arrays for objtypes | Tristan Gingold | 2022-05-22 | 6 | -58/+66 |
| * | synth: merge value for type_vector and type_array | Tristan Gingold | 2022-05-22 | 15 | -137/+113 |
| * | elab-vhdl_values-debug: improve debug_typ output | Tristan Gingold | 2022-05-22 | 1 | -14/+37 |
| * | synth: use unidimentional arrays in type_acc. Factorize code. | Tristan Gingold | 2022-05-22 | 17 | -552/+340 |
| * | synth-vhdl_stmts: write generic procedure Assign_Aggregate. | Tristan Gingold | 2022-05-21 | 2 | -14/+29 |
| * | synth-vhdl_expr: avoid a memocy copy | Tristan Gingold | 2022-05-21 | 1 | -3/+7 |
| * | vhdl-canon: remove unused canon_flag_inertial_associations | Tristan Gingold | 2022-05-20 | 3 | -9/+0 |
| * | synth/elab-vhdl_values: use a proper type for signal_index | Tristan Gingold | 2022-05-19 | 5 | -7/+11 |
| * | synth-vhdl_stmts: avoid a crash after an error. Fix #2063 | Tristan Gingold | 2022-05-18 | 1 | -1/+4 |
| * | synth-vhdl_stmts: add comments about report statements | Tristan Gingold | 2022-05-18 | 1 | -5/+51 |
