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* vhdl: recognize minus from std_logic_unsignedTristan Gingold2019-10-113-1/+17
* vhdl: do not try to recognize mentor version of std_logic_arith.Tristan Gingold2019-10-101-0/+7
* synth: remove synth-typesTristan Gingold2019-10-104-91/+13
* netlists: add internings child package.Tristan Gingold2019-10-103-14/+61
* ghdlsynth: add --out=none to not display the result.Tristan Gingold2019-10-101-1/+6
* netlists-disp_vhdl: fix pasto on id_asr.Tristan Gingold2019-10-101-5/+5
* vhdl: improve error message for redefinition of libraryTristan Gingold2019-10-101-1/+1
* synth: handle constants for enum equality.Tristan Gingold2019-10-101-1/+5
* netlists: give a name to the free module.Tristan Gingold2019-10-101-2/+4
* synth: rewrite cleanup pass.Tristan Gingold2019-10-107-68/+188
* synth-decls: ignore use clauses.Tristan Gingold2019-10-101-0/+2
* synth-opeer: extend synth_uresizeTristan Gingold2019-10-101-1/+1
* synth-oper: handle more operators.Tristan Gingold2019-10-101-3/+6
* vhdl: recognize conv_unsigned from ieee.std_logic_arith.Tristan Gingold2019-10-106-4/+206
* synth: set name on generate statements.Tristan Gingold2019-10-092-6/+16
* synth: set location on instances.Tristan Gingold2019-10-091-0/+1
* synth: use synth.source for setting location.Tristan Gingold2019-10-098-17/+34
* netlists-disp_vhdl: handle const_SB32Tristan Gingold2019-10-091-1/+2
* synth-environment: fix a thinko.Tristan Gingold2019-10-091-1/+2
* synth: improve support of procedure calls.Tristan Gingold2019-10-081-20/+25
* synth: handle read-only aliases. Fix #973Tristan Gingold2019-10-081-1/+9
* synth-context: fix encoding of discrete in aggregateTristan Gingold2019-10-081-1/+1
* synth-disp_vhdl: fix incorrect code for record of widthTristan Gingold2019-10-081-1/+3
* synth: fix mul sgn sgn width.Tristan Gingold2019-10-082-8/+9
* synth: fix incorrect order for concat.Tristan Gingold2019-10-082-3/+6
* synth-disp_vhdl: handle array/record of 1 element.Tristan Gingold2019-10-081-3/+11
* synth: handle subprograms in package body.Tristan Gingold2019-10-081-0/+5
* synth: infere_ff: handle pre-enable. Fix #964Tristan Gingold2019-10-081-23/+63
* synth: handle case statement on bit vectors.Tristan Gingold2019-10-071-0/+23
* synth: handle package bodies.Tristan Gingold2019-10-077-9/+70
* synth-oper: handle to_bitvector, simplify.Tristan Gingold2019-10-071-9/+18
* vhdl: recognize to_bitvector.Tristan Gingold2019-10-074-84/+79
* ghdlsynth: setup error messages for netlists.Tristan Gingold2019-10-071-0/+2
* synth-disp_vhdl: handle enum of width 1 forTristan Gingold2019-10-071-2/+6
* synth-oper: add support for more functions.Tristan Gingold2019-10-071-1/+51
* synth: preliminary support for user packages.Tristan Gingold2019-10-074-84/+85
* synth: allow unconnected port.Tristan Gingold2019-10-071-5/+7
* ghdlsynth: add --out=dumpTristan Gingold2019-10-071-1/+7
* synth: add support for concurrent procedure calls. Fix #969Tristan Gingold2019-10-072-4/+9
* synth: propagate assignments out of subprograms. Fix #960Tristan Gingold2019-10-063-2/+43
* netlists-dump: improve output for --out=rawTristan Gingold2019-10-061-4/+5
* synth: revert patch on synth_subprogram_association.Tristan Gingold2019-10-063-8/+4
* synth: handle subtypes in components. Fix #970Tristan Gingold2019-10-064-20/+61
* ghdlsynth: fix crash when using libghdl.Tristan Gingold2019-10-063-3/+5
* synth: fix crash for port subtype in component.Tristan Gingold2019-10-061-1/+1
* synth: handle /= with non-matching length. For #968Tristan Gingold2019-10-061-6/+10
* netlists: remove get_parent for instance.Tristan Gingold2019-10-061-2/+0
* netlists: remove get_parent renaming for input.Tristan Gingold2019-10-065-6/+5
* netlists: remove renaming of Get_Parent for Net.Tristan Gingold2019-10-0612-33/+34
* netlists: remove get_name renaming for modules.Tristan Gingold2019-10-064-9/+8
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