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| author | Tristan Gingold <tgingold@free.fr> | 2019-10-11 06:21:24 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2019-10-11 06:21:24 +0200 |
| commit | 2714a30c3753c76cda95eb994851a8be95e60ad9 (patch) | |
| tree | ed759d92892d21a21cc5e60e2995e9feef5ed1a2 /src | |
| parent | f4be996776af67b5242e9ec5fc18ec1fe27d0efb (diff) | |
| download | ghdl-2714a30c3753c76cda95eb994851a8be95e60ad9.tar.gz ghdl-2714a30c3753c76cda95eb994851a8be95e60ad9.tar.bz2 ghdl-2714a30c3753c76cda95eb994851a8be95e60ad9.zip | |
vhdl: recognize minus from std_logic_unsigned
Diffstat (limited to 'src')
| -rw-r--r-- | src/synth/synth-oper.adb | 3 | ||||
| -rw-r--r-- | src/vhdl/vhdl-ieee-std_logic_unsigned.adb | 9 | ||||
| -rw-r--r-- | src/vhdl/vhdl-nodes.ads | 6 |
3 files changed, 17 insertions, 1 deletions
diff --git a/src/synth/synth-oper.adb b/src/synth/synth-oper.adb index bdea830f1..62bc1a51e 100644 --- a/src/synth/synth-oper.adb +++ b/src/synth/synth-oper.adb @@ -507,7 +507,8 @@ package body Synth.Oper is -- "+" (Signed, Signed) return Synth_Dyadic_Sgn (Id_Add, True); - when Iir_Predefined_Ieee_Numeric_Std_Sub_Uns_Nat => + when Iir_Predefined_Ieee_Numeric_Std_Sub_Uns_Nat + | Iir_Predefined_Ieee_Std_Logic_Unsigned_Sub_Slv_Int => -- "-" (Unsigned, Natural) return Synth_Dyadic_Uns_Nat (Id_Sub); when Iir_Predefined_Ieee_Numeric_Std_Sub_Uns_Uns => diff --git a/src/vhdl/vhdl-ieee-std_logic_unsigned.adb b/src/vhdl/vhdl-ieee-std_logic_unsigned.adb index dafbf7dad..7e2b86c02 100644 --- a/src/vhdl/vhdl-ieee-std_logic_unsigned.adb +++ b/src/vhdl/vhdl-ieee-std_logic_unsigned.adb @@ -58,6 +58,13 @@ package body Vhdl.Ieee.Std_Logic_Unsigned is Arg_Slv_Sl => Iir_Predefined_Ieee_Std_Logic_Unsigned_Add_Slv_Sl, Arg_Sl_Slv => Iir_Predefined_Ieee_Std_Logic_Unsigned_Add_Sl_Slv); + Sub_Patterns : constant Binary_Pattern_Type := + (Arg_Slv_Slv => Iir_Predefined_Ieee_Std_Logic_Unsigned_Sub_Slv_Slv, + Arg_Slv_Int => Iir_Predefined_Ieee_Std_Logic_Unsigned_Sub_Slv_Int, + Arg_Int_Slv => Iir_Predefined_Ieee_Std_Logic_Unsigned_Sub_Int_Slv, + Arg_Slv_Sl => Iir_Predefined_Ieee_Std_Logic_Unsigned_Sub_Slv_Sl, + Arg_Sl_Slv => Iir_Predefined_Ieee_Std_Logic_Unsigned_Sub_Sl_Slv); + Error : exception; procedure Extract_Declarations (Pkg : Iir_Package_Declaration) @@ -140,6 +147,8 @@ package body Vhdl.Ieee.Std_Logic_Unsigned is Handle_Binary (Le_Patterns); when Name_Op_Plus => Handle_Binary (Add_Patterns); + when Name_Op_Minus => + Handle_Binary (Sub_Patterns); when others => null; end case; diff --git a/src/vhdl/vhdl-nodes.ads b/src/vhdl/vhdl-nodes.ads index 840f0bb70..f903a4c4d 100644 --- a/src/vhdl/vhdl-nodes.ads +++ b/src/vhdl/vhdl-nodes.ads @@ -5063,6 +5063,12 @@ package Vhdl.Nodes is Iir_Predefined_Ieee_Std_Logic_Unsigned_Add_Slv_Sl, Iir_Predefined_Ieee_Std_Logic_Unsigned_Add_Sl_Slv, + Iir_Predefined_Ieee_Std_Logic_Unsigned_Sub_Slv_Slv, + Iir_Predefined_Ieee_Std_Logic_Unsigned_Sub_Slv_Int, + Iir_Predefined_Ieee_Std_Logic_Unsigned_Sub_Int_Slv, + Iir_Predefined_Ieee_Std_Logic_Unsigned_Sub_Slv_Sl, + Iir_Predefined_Ieee_Std_Logic_Unsigned_Sub_Sl_Slv, + Iir_Predefined_Ieee_Std_Logic_Unsigned_Lt_Slv_Slv, Iir_Predefined_Ieee_Std_Logic_Unsigned_Lt_Slv_Int, Iir_Predefined_Ieee_Std_Logic_Unsigned_Lt_Int_Slv, |