aboutsummaryrefslogtreecommitdiffstats
path: root/src/synth
Commit message (Collapse)AuthorAgeFilesLines
...
* synth: add support for nested packagesTristan Gingold2023-01-023-19/+87
|
* synth: elaborate case generate statementsTristan Gingold2023-01-015-17/+72
|
* simul: handle nested packagesTristan Gingold2023-01-012-0/+14
|
* elab-vhdl_expr: fix a crash on simple aggregateTristan Gingold2022-12-311-8/+2
|
* synth: handle string literals in debugTristan Gingold2022-12-311-1/+2
|
* synth: add statement in context, adjust path/instance name attributesTristan Gingold2022-12-319-42/+91
|
* synth: check bounds for pos and val attributesTristan Gingold2022-12-261-3/+10
|
* synth: improve support of value attributeTristan Gingold2022-12-261-3/+36
|
* simul: handle driving and driving_value attributesTristan Gingold2022-12-262-0/+15
|
* synth: handle instance_name attributeTristan Gingold2022-12-265-9/+115
|
* synth: add support for numeric_std_unsigned add, sub, fix #2286tmeissner2022-12-261-2/+8
|
* synth: add support for to_x01z. Fix #2285Tristan Gingold2022-12-261-1/+3
|
* simul: allow unassigned top genericsTristan Gingold2022-12-261-2/+8
|
* synth: add value_sig_val to handle individual signal associationsTristan Gingold2022-12-2611-23/+128
|
* synth-vhdl_stmts(Aggregate_Array_Extract): fix offset for vector extractionTristan Gingold2022-12-261-1/+2
|
* synth: handle element in target aggregate. Fix #2279Tristan Gingold2022-12-221-3/+7
|
* synth: factorize code (Exec_Name_Subtype). Fix #2273Tristan Gingold2022-12-184-84/+26
|
* Restore latch inference.cderrien2022-12-161-5/+1
|
* synth-vhdl_stmts: handle impure functions.Tristan Gingold2022-12-161-1/+8
| | | | Fix #2270
* synth-vhdl_eval: minor refactoringTristan Gingold2022-11-301-32/+38
|
* synth-vhdl_oper: handle more operators.Tristan Gingold2022-11-301-51/+131
|
* synth-vhdl_oper: complete rework on predefined functions.Tristan Gingold2022-11-302-645/+571
| | | | The same subprogram now handle all the predefined functions.
* synth-vhdl_oper: refactoringTristan Gingold2022-11-301-61/+86
|
* synth-vhdl_eval(eval_static_predefined_function_call): handle all operationsTristan Gingold2022-11-283-983/+953
|
* synth: improve error message for ghdl/ghdl-yosys-plugin#179Tristan Gingold2022-11-151-1/+3
|
* synth: avoid a crash on signal assignment in non-sensitized process.Tristan Gingold2022-11-141-2/+9
| | | | Fix ghdl/ghdl-yosys-plugin#180
* Remove trailing spacesTristan Gingold2022-11-081-1/+1
|
* elab-vhdl_expr: fix a crash on simple aggregates. Fix #2240Tristan Gingold2022-11-082-15/+13
|
* Added id to warnings related to attributes. (#2242)cderrien2022-11-084-2/+20
|
* Escape port name in dot output. (#2241)cderrien2022-11-081-1/+1
|
* netlists-memories: refactoringTristan Gingold2022-11-061-113/+105
|
* netlists-memories: factorize code.Tristan Gingold2022-11-061-83/+41
|
* netlists: factorize codeTristan Gingold2022-11-061-100/+56
|
* synth-environment.adb: fix warningTristan Gingold2022-11-051-1/+0
|
* synth: rework memory inference. Fix #2232Tristan Gingold2022-11-053-78/+233
|
* netlists-builders: allow building mem_wr_sync without clk and en.Tristan Gingold2022-11-051-4/+10
|
* synth: infere a dff (instead of an idff) when the init value is XTristan Gingold2022-11-032-6/+21
|
* synth: handle bit/unsigned and bit/signed vhdl 08 operators.Tristan Gingold2022-11-021-12/+36
| | | | Fix #2237
* netlists-inference: handle flip-flop with different patterns.Tristan Gingold2022-10-301-23/+75
| | | | Fix #2231
* netlists-gates: add a commentTristan Gingold2022-10-301-0/+1
|
* synth: internal refactoringTristan Gingold2022-10-294-121/+93
| | | | use memtyp for eval_static_predefined_function_call
* elab-vhdl_types: abstract elab_floating_type_definitionTristan Gingold2022-10-291-10/+15
|
* synth: fix crash in disp_verilog. Fix #2234Tristan Gingold2022-10-291-3/+8
|
* synth: handle copyback associations in any order.Tristan Gingold2022-10-191-12/+30
|
* synth-vhdl_eval: handle std_logic_misc reduce functionsTristan Gingold2022-10-191-0/+27
|
* synth-vhdl_oper: handle xor/nand/nor/xnor reduce from std_logic_miscTristan Gingold2022-10-191-16/+34
|
* synth-vhdl_oper: handle and_reduce. Fix #2224Tristan Gingold2022-10-191-1/+10
|
* synth: extract elab-vhdl_utils from synth-vhdl_stmts.Tristan Gingold2022-10-183-142/+241
| | | | Fix #2222
* synth: handle record conversionTristan Gingold2022-10-141-0/+3
|
* synth-vhdl_expr: support alias in indexed namesTristan Gingold2022-10-141-1/+2
|
generated by cgit v1.2.3 (git 2.25.1) at 2025-04-05 21:55:34 +0000