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| author | Tristan Gingold <tgingold@free.fr> | 2022-10-29 10:20:54 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2022-10-29 10:20:54 +0200 |
| commit | 36b19897aea1140b0e988fed620ac2597b3b2440 (patch) | |
| tree | 083c3333bea8a88378b4c83ee33e6c5d6e366739 /src/synth | |
| parent | eb0ae738e7fbf3301b2a492e5fbabca3c3bdda50 (diff) | |
| download | ghdl-36b19897aea1140b0e988fed620ac2597b3b2440.tar.gz ghdl-36b19897aea1140b0e988fed620ac2597b3b2440.tar.bz2 ghdl-36b19897aea1140b0e988fed620ac2597b3b2440.zip | |
synth: fix crash in disp_verilog. Fix #2234
Diffstat (limited to 'src/synth')
| -rw-r--r-- | src/synth/netlists-disp_verilog.adb | 11 |
1 files changed, 8 insertions, 3 deletions
diff --git a/src/synth/netlists-disp_verilog.adb b/src/synth/netlists-disp_verilog.adb index 1ab834fe9..93e572982 100644 --- a/src/synth/netlists-disp_verilog.adb +++ b/src/synth/netlists-disp_verilog.adb @@ -718,9 +718,14 @@ package body Netlists.Disp_Verilog is begin Val := Get_Input_Net (Mem, 1); Val_Inst := Get_Net_Parent (Val); - if Get_Id (Val_Inst) = Id_Isignal then - Val := Get_Input_Net (Val_Inst, 1); - end if; + case Get_Id (Val_Inst) is + when Id_Isignal => + Val := Get_Input_Net (Val_Inst, 1); + when Id_Signal => + Val := Get_Input_Net (Val_Inst, 0); + when others => + null; + end case; Disp_Memory_Init (Mem, Val, Data_W, Depth); end; end if; |