synth-vhdl_eval(eval_static_predefined_function_call): handle all operations

3 files changed, 953 insertions, 983 deletions

diff --git a/src/synth/synth-vhdl_eval.adb b/src/synth/synth-vhdl_eval.adb
index 1f60fd1a2..f5be3d91d 100644
--- a/src/synth/synth-vhdl_eval.adb
+++ b/src/synth/synth-vhdl_eval.adb
@@ -419,13 +419,484 @@ package body Synth.Vhdl_Eval is
       return Create_Memory_U8 (Boolean'Pos (V), Boolean_Type);
    end Create_Memory_Boolean;
 
-   function Eval_Static_Dyadic_Predefined (Inst : Synth_Instance_Acc;
-                                           Imp : Node;
-                                           Res_Typ : Type_Acc;
-                                           Left : Memtyp;
-                                           Right : Memtyp;
-                                           Expr : Node) return Memtyp
+   function Eval_Vector_Monadic (Vec : Memtyp; Op : Table_1d) return Memtyp
+   is
+      Len : constant Iir_Index32 := Vec_Length (Vec.Typ);
+      Res : Memtyp;
+   begin
+      Res := Create_Memory (Create_Res_Bound (Vec.Typ));
+      for I in 1 .. Uns32 (Len) loop
+         declare
+            V : constant Std_Ulogic := Read_Std_Logic (Vec.Mem, I - 1);
+         begin
+            Write_Std_Logic (Res.Mem, I - 1, Op (V));
+         end;
+      end loop;
+      return Res;
+   end Eval_Vector_Monadic;
+
+   function Eval_Vector_Reduce (Init : Std_Ulogic;
+                                Vec : Memtyp;
+                                Op : Table_2d;
+                                Neg : Boolean) return Memtyp
+   is
+      El_Typ : constant Type_Acc := Vec.Typ.Arr_El;
+      Res : Std_Ulogic;
+   begin
+      Res := Init;
+      for I in 1 .. Uns32 (Vec_Length (Vec.Typ)) loop
+         declare
+            V : constant Std_Ulogic := Read_Std_Logic (Vec.Mem, I - 1);
+         begin
+            Res := Op (Res, V);
+         end;
+      end loop;
+
+      if Neg then
+         Res := Not_Table (Res);
+      end if;
+
+      return Create_Memory_U8 (Std_Ulogic'Pos (Res), El_Typ);
+   end Eval_Vector_Reduce;
+
+   function Eval_TF_Vector_Monadic (Vec : Memtyp) return Memtyp
+   is
+      Len : constant Iir_Index32 := Vec_Length (Vec.Typ);
+      Res : Memtyp;
+   begin
+      Res := Create_Memory (Create_Res_Bound (Vec.Typ));
+      for I in 1 .. Uns32 (Len) loop
+         declare
+            V : constant Boolean :=
+              Boolean'Val (Read_U8 (Vec.Mem + Size_Type (I - 1)));
+         begin
+            Write_U8 (Res.Mem + Size_Type (I - 1), Boolean'Pos (not V));
+         end;
+      end loop;
+      return Res;
+   end Eval_TF_Vector_Monadic;
+
+   function Eval_TF_Vector_Reduce (Init : Boolean;
+                                   Neg : Boolean;
+                                   Vec : Memtyp;
+                                   Op : Tf_Table_2d) return Memtyp
    is
+      El_Typ : constant Type_Acc := Vec.Typ.Arr_El;
+      Res : Boolean;
+   begin
+      Res := Init;
+      for I in 1 .. Size_Type (Vec.Typ.Abound.Len) loop
+         declare
+            V : constant Boolean := Boolean'Val (Read_U8 (Vec.Mem + (I - 1)));
+         begin
+            Res := Op (Res, V);
+         end;
+      end loop;
+
+      return Create_Memory_U8 (Boolean'Pos (Res xor Neg), El_Typ);
+   end Eval_TF_Vector_Reduce;
+
+   function Eval_Vector_Maximum (Vec : Memtyp) return Memtyp
+   is
+      Etyp : constant Type_Acc := Vec.Typ.Arr_El;
+      Len : constant Uns32 := Vec.Typ.Abound.Len;
+   begin
+      case Etyp.Kind is
+         when Type_Logic
+           | Type_Bit
+           | Type_Discrete =>
+            declare
+               Res : Int64;
+               V : Int64;
+            begin
+               case Etyp.Drange.Dir is
+                  when Dir_To =>
+                     Res := Etyp.Drange.Left;
+                  when Dir_Downto =>
+                     Res := Etyp.Drange.Right;
+               end case;
+
+               for I in 1 .. Len loop
+                  V := Read_Discrete
+                    (Vec.Mem + Size_Type (I - 1) * Etyp.Sz, Etyp);
+                  if V > Res then
+                     Res := V;
+                  end if;
+               end loop;
+               return Create_Memory_Discrete (Res, Etyp);
+            end;
+         when Type_Float =>
+            declare
+               Res : Fp64;
+               V : Fp64;
+            begin
+               case Etyp.Frange.Dir is
+                  when Dir_To =>
+                     Res := Etyp.Frange.Left;
+                  when Dir_Downto =>
+                     Res := Etyp.Frange.Right;
+               end case;
+
+               for I in 1 .. Len loop
+                  V := Read_Fp64
+                    (Vec.Mem + Size_Type (I - 1) * Etyp.Sz);
+                  if V > Res then
+                     Res := V;
+                  end if;
+               end loop;
+               return Create_Memory_Fp64 (Res, Etyp);
+            end;
+         when others =>
+            raise Internal_Error;
+      end case;
+   end Eval_Vector_Maximum;
+
+   function Eval_Vector_Minimum (Vec : Memtyp) return Memtyp
+   is
+      Etyp : constant Type_Acc := Vec.Typ.Arr_El;
+      Len : constant Uns32 := Vec.Typ.Abound.Len;
+   begin
+      case Etyp.Kind is
+         when Type_Logic
+           | Type_Bit
+           | Type_Discrete =>
+            declare
+               Res : Int64;
+               V : Int64;
+            begin
+               case Etyp.Drange.Dir is
+                  when Dir_To =>
+                     Res := Etyp.Drange.Right;
+                  when Dir_Downto =>
+                     Res := Etyp.Drange.Left;
+               end case;
+
+               for I in 1 .. Len loop
+                  V := Read_Discrete
+                    (Vec.Mem + Size_Type (I - 1) * Etyp.Sz, Etyp);
+                  if V < Res then
+                     Res := V;
+                  end if;
+               end loop;
+               return Create_Memory_Discrete (Res, Etyp);
+            end;
+         when Type_Float =>
+            declare
+               Res : Fp64;
+               V : Fp64;
+            begin
+               case Etyp.Frange.Dir is
+                  when Dir_To =>
+                     Res := Etyp.Frange.Right;
+                  when Dir_Downto =>
+                     Res := Etyp.Frange.Left;
+               end case;
+
+               for I in 1 .. Len loop
+                  V := Read_Fp64
+                    (Vec.Mem + Size_Type (I - 1) * Etyp.Sz);
+                  if V < Res then
+                     Res := V;
+                  end if;
+               end loop;
+               return Create_Memory_Fp64 (Res, Etyp);
+            end;
+         when others =>
+            raise Internal_Error;
+      end case;
+   end Eval_Vector_Minimum;
+
+   function Eval_To_Log_Vector (Arg : Uns64; Sz : Int64; Res_Type : Type_Acc)
+                               return Memtyp
+   is
+      Len : constant Iir_Index32 := Iir_Index32 (Sz);
+      El_Type : constant Type_Acc := Get_Array_Element (Res_Type);
+      Res : Memtyp;
+      Bnd : Type_Acc;
+      B : Uns64;
+   begin
+      Bnd := Create_Vec_Type_By_Length (Width (Len), El_Type);
+      Res := Create_Memory (Bnd);
+      for I in 1 .. Len loop
+         B := Shift_Right_Arithmetic (Arg, Natural (I - 1)) and 1;
+         Write_Std_Logic (Res.Mem, Uns32 (Len - I),
+                          Std_Ulogic'Val (Std_Logic_0_Pos + B));
+      end loop;
+      return Res;
+   end Eval_To_Log_Vector;
+
+   function Eval_To_Bit_Vector (Arg : Uns64; Sz : Int64; Res_Type : Type_Acc)
+                               return Memtyp
+   is
+      Len : constant Size_Type := Size_Type (Sz);
+      El_Type : constant Type_Acc := Get_Array_Element (Res_Type);
+      Res : Memtyp;
+      Bnd : Type_Acc;
+      B : Uns64;
+   begin
+      Bnd := Create_Vec_Type_By_Length (Width (Sz), El_Type);
+      Res := Create_Memory (Bnd);
+      for I in 1 .. Len loop
+         B := Shift_Right_Arithmetic (Arg, Natural (I - 1)) and 1;
+         Write_U8 (Res.Mem + (Len - I), Ghdl_U8 (B));
+      end loop;
+      return Res;
+   end Eval_To_Bit_Vector;
+
+   function Eval_Unsigned_To_Integer (Arg : Memtyp; Loc : Node) return Int64
+   is
+      Res : Uns64;
+      V : Std_Ulogic;
+   begin
+      Res := 0;
+      for I in 1 .. Vec_Length (Arg.Typ) loop
+         V := Std_Ulogic'Val (Read_U8 (Arg.Mem + Size_Type (I - 1)));
+         case To_X01 (V) is
+            when '0' =>
+               Res := Res * 2;
+            when '1' =>
+               Res := Res * 2 + 1;
+            when 'X' =>
+               Warning_Msg_Synth
+                 (+Loc, "metavalue detected, returning 0");
+               Res := 0;
+               exit;
+         end case;
+      end loop;
+      return To_Int64 (Res);
+   end Eval_Unsigned_To_Integer;
+
+   function Eval_Signed_To_Integer (Arg : Memtyp; Loc : Node) return Int64
+   is
+      Len : constant Iir_Index32 := Vec_Length (Arg.Typ);
+      Res : Uns64;
+      E : Std_Ulogic;
+   begin
+      if Len = 0 then
+         Warning_Msg_Synth
+           (+Loc, "numeric_std.to_integer: null detected, returning 0");
+         return 0;
+      end if;
+
+      E := Std_Ulogic'Val (Read_U8 (Arg.Mem));
+      case To_X01 (E) is
+         when '0' =>
+            Res := 0;
+         when '1' =>
+            Res := not 0;
+         when 'X' =>
+            Warning_Msg_Synth (+Loc, "metavalue detected, returning 0");
+            return 0;
+      end case;
+      for I in 2 .. Len loop
+         E := Std_Ulogic'Val (Read_U8 (Arg.Mem + Size_Type (I - 1)));
+         case To_X01 (E) is
+            when '0' =>
+               Res := Res * 2;
+            when '1' =>
+               Res := Res * 2 + 1;
+            when 'X' =>
+               Warning_Msg_Synth (+Loc, "metavalue detected, returning 0");
+               return 0;
+         end case;
+      end loop;
+      return To_Int64 (Res);
+   end Eval_Signed_To_Integer;
+
+   function Eval_Array_Char_To_String (Param : Memtyp;
+                                       Res_Typ : Type_Acc;
+                                       Imp : Node) return Memtyp
+   is
+      use Vhdl.Utils;
+      use Name_Table;
+      Len : constant Uns32 := Param.Typ.Abound.Len;
+      Elt : constant Type_Acc := Param.Typ.Arr_El;
+      Etype : constant Node := Get_Base_Type
+        (Get_Element_Subtype
+           (Get_Type (Get_Interface_Declaration_Chain (Imp))));
+      pragma Assert (Get_Kind (Etype) = Iir_Kind_Enumeration_Type_Definition);
+      Enums : constant Iir_Flist := Get_Enumeration_Literal_List (Etype);
+      Lit : Node;
+      Lit_Id : Name_Id;
+      Bnd : Bound_Type;
+      Res_St : Type_Acc;
+      Res : Memtyp;
+      V : Int64;
+   begin
+      Bnd := Elab.Vhdl_Types.Create_Bounds_From_Length
+        (Res_Typ.Uarr_Idx.Drange, Iir_Index32 (Len));
+      Res_St := Create_Onedimensional_Array_Subtype
+        (Res_Typ, Bnd, Res_Typ.Uarr_El);
+      Res := Create_Memory (Res_St);
+      for I in 1 .. Len loop
+         V := Read_Discrete (Param.Mem + Size_Type (I - 1) * Elt.Sz, Elt);
+         Lit := Get_Nth_Element (Enums, Natural (V));
+         Lit_Id := Get_Identifier (Lit);
+         pragma Assert (Is_Character (Lit_Id));
+         Write_U8 (Res.Mem + Size_Type (I - 1),
+                   Character'Pos (Get_Character (Lit_Id)));
+      end loop;
+      return Res;
+   end Eval_Array_Char_To_String;
+
+   function String_To_Memtyp (Str : String; Styp : Type_Acc) return Memtyp
+   is
+      Len : constant Natural := Str'Length;
+      Bnd : Bound_Type;
+      Typ : Type_Acc;
+      Res : Memtyp;
+   begin
+      Bnd := (Dir => Dir_To, Left => 1, Right => Int32 (Len),
+              Len => Uns32 (Len));
+      Typ := Create_Array_Type (Bnd, True, Styp.Uarr_El);
+
+      Res := Create_Memory (Typ);
+      for I in Str'Range loop
+         Write_U8 (Res.Mem + Size_Type (I - Str'First),
+                   Character'Pos (Str (I)));
+      end loop;
+      return Res;
+   end String_To_Memtyp;
+
+   function Eval_Enum_To_String (Param : Memtyp;
+                                 Res_Typ : Type_Acc;
+                                 Imp : Node) return Memtyp
+   is
+      use Vhdl.Utils;
+      use Name_Table;
+      Etype : constant Node := Get_Base_Type
+        (Get_Type (Get_Interface_Declaration_Chain (Imp)));
+      pragma Assert (Get_Kind (Etype) = Iir_Kind_Enumeration_Type_Definition);
+      Enums : constant Iir_Flist := Get_Enumeration_Literal_List (Etype);
+      Lit : Node;
+      Lit_Id : Name_Id;
+      V : Int64;
+      C : String (1 .. 1);
+   begin
+      V := Read_Discrete (Param.Mem, Param.Typ);
+      Lit := Get_Nth_Element (Enums, Natural (V));
+      Lit_Id := Get_Identifier (Lit);
+      if Is_Character (Lit_Id) then
+         C (1) := Get_Character (Lit_Id);
+         return String_To_Memtyp (C, Res_Typ);
+      else
+         return String_To_Memtyp (Image (Lit_Id), Res_Typ);
+      end if;
+   end Eval_Enum_To_String;
+
+   Hex_Chars : constant array (Natural range 0 .. 15) of Character :=
+     "0123456789ABCDEF";
+
+   function Eval_Bit_Vector_To_String (Val : Memtyp;
+                                       Res_Typ : Type_Acc;
+                                       Log_Base : Natural) return Memtyp
+   is
+      Base : constant Natural := 2 ** Log_Base;
+      Blen : constant Natural := Natural (Val.Typ.Abound.Len);
+      Str : String (1 .. (Blen + Log_Base - 1) / Log_Base);
+      Pos : Natural;
+      V : Natural;
+      N : Natural;
+   begin
+      V := 0;
+      N := 1;
+      Pos := Str'Last;
+      for I in 1 .. Blen loop
+         V := V + Natural (Read_U8 (Val.Mem + Size_Type (Blen - I))) * N;
+         N := N * 2;
+         if N = Base or else I = Blen then
+            Str (Pos) := Hex_Chars (V);
+            Pos := Pos - 1;
+            N := 1;
+            V := 0;
+         end if;
+      end loop;
+      return String_To_Memtyp (Str, Res_Typ);
+   end Eval_Bit_Vector_To_String;
+
+   function Eval_Logic_Vector_To_String (Val : Memtyp;
+                                         Res_Typ : Type_Acc;
+                                         Is_Signed : Boolean;
+                                         Log_Base : Natural) return Memtyp
+   is
+      Base : constant Natural := 2 ** Log_Base;
+      Blen : constant Uns32 := Val.Typ.Abound.Len;
+      Str : String (1 .. (Natural (Blen) + Log_Base - 1) / Log_Base);
+      Pos : Natural;
+      D : Std_Ulogic;
+      V : Natural;
+      N : Natural;
+      Has_X, Has_Z, Has_D : Boolean;
+   begin
+      V := 0;
+      N := 1;
+      Has_X := False;
+      Has_Z := False;
+      Has_D := False;
+      Pos := Str'Last;
+      for I in 1 .. Blen loop
+         D := Read_Std_Logic (Val.Mem, Blen - I);
+         case D is
+            when '0' | 'L' =>
+               Has_D := True;
+            when '1' | 'H' =>
+               Has_D := True;
+               V := V + N;
+            when 'Z' | 'W' =>
+               Has_Z := True;
+            when 'X' | 'U' | '-' =>
+               Has_X := True;
+         end case;
+         N := N * 2;
+         if N = Base or else I = Blen then
+            if Has_X or (Has_Z and Has_D) then
+               Str (Pos) := 'X';
+            elsif Has_Z then
+               Str (Pos) := 'Z';
+            else
+               if Is_Signed and N < Base and (D = '1' or D = 'H') then
+                  --  Sign extend.
+                  loop
+                     V := V + N;
+                     N := N * 2;
+                     exit when N = Base;
+                  end loop;
+               end if;
+               Str (Pos) := Hex_Chars (V);
+            end if;
+            Pos := Pos - 1;
+            N := 1;
+            V := 0;
+            Has_X := False;
+            Has_Z := False;
+            Has_D := False;
+         end if;
+      end loop;
+      return String_To_Memtyp (Str, Res_Typ);
+   end Eval_Logic_Vector_To_String;
+
+   function Eval_To_X01 (Val : Memtyp; Map : Table_1d) return Memtyp
+   is
+      Len : constant Uns32 := Val.Typ.Abound.Len;
+      Res : Memtyp;
+      B : Std_Ulogic;
+   begin
+      Res := Create_Memory (Create_Res_Bound (Val.Typ));
+      for I in 1 .. Len loop
+         B := Read_Std_Logic (Val.Mem, I - 1);
+         B := Map (B);
+         Write_Std_Logic (Res.Mem, I - 1, B);
+      end loop;
+      return Res;
+   end Eval_To_X01;
+
+   function Eval_Static_Predefined_Function_Call (Inst : Synth_Instance_Acc;
+                                                  Param1 : Memtyp;
+                                                  Param2 : Memtyp;
+                                                  Res_Typ : Type_Acc;
+                                                  Expr : Node) return Memtyp
+   is
+      Imp  : constant Node := Get_Implementation (Expr);
       Def : constant Iir_Predefined_Functions :=
         Get_Implicit_Definition (Imp);
    begin
@@ -433,6 +904,124 @@ package body Synth.Vhdl_Eval is
          when Iir_Predefined_Error =>
             return Null_Memtyp;
 
+         when Iir_Predefined_Boolean_Not
+           | Iir_Predefined_Bit_Not =>
+            return Create_Memory_U8 (1 - Read_U8 (Param1), Param1.Typ);
+
+         when Iir_Predefined_Bit_Condition =>
+            return Create_Memory_U8 (Read_U8 (Param1), Param1.Typ);
+
+         when Iir_Predefined_Integer_Negation
+           | Iir_Predefined_Physical_Negation =>
+            return Create_Memory_Discrete
+              (-Read_Discrete (Param1), Param1.Typ);
+         when Iir_Predefined_Integer_Absolute
+           | Iir_Predefined_Physical_Absolute =>
+            return Create_Memory_Discrete
+              (abs Read_Discrete (Param1), Param1.Typ);
+         when Iir_Predefined_Integer_Identity
+           | Iir_Predefined_Physical_Identity =>
+            return Param1;
+
+         when Iir_Predefined_Floating_Negation =>
+            return Create_Memory_Fp64 (-Read_Fp64 (Param1), Param1.Typ);
+         when Iir_Predefined_Floating_Identity =>
+            return Param1;
+         when Iir_Predefined_Floating_Absolute =>
+            return Create_Memory_Fp64 (abs Read_Fp64 (Param1), Param1.Typ);
+
+         when Iir_Predefined_Vector_Maximum =>
+            return Eval_Vector_Maximum (Param1);
+         when Iir_Predefined_Vector_Minimum =>
+            return Eval_Vector_Minimum (Param1);
+
+         when Iir_Predefined_TF_Array_Not =>
+            return Eval_TF_Vector_Monadic (Param1);
+
+         when Iir_Predefined_TF_Reduction_Or =>
+            return Eval_TF_Vector_Reduce (False, False, Param1, Tf_2d_Or);
+         when Iir_Predefined_TF_Reduction_And =>
+            return Eval_TF_Vector_Reduce (True, False, Param1, Tf_2d_And);
+         when Iir_Predefined_TF_Reduction_Xor =>
+            return Eval_TF_Vector_Reduce (False, False, Param1, Tf_2d_Xor);
+         when Iir_Predefined_TF_Reduction_Nor =>
+            return Eval_TF_Vector_Reduce (False, True, Param1, Tf_2d_Or);
+         when Iir_Predefined_TF_Reduction_Nand =>
+            return Eval_TF_Vector_Reduce (True, True, Param1, Tf_2d_And);
+         when Iir_Predefined_TF_Reduction_Xnor =>
+            return Eval_TF_Vector_Reduce (False, True, Param1, Tf_2d_Xor);
+
+         when Iir_Predefined_Ieee_1164_Condition_Operator =>
+            --  Constant std_logic: need to convert.
+            declare
+               Val : Uns32;
+               Zx : Uns32;
+            begin
+               From_Std_Logic (Int64 (Read_U8 (Param1)), Val, Zx);
+               return Create_Memory_U8
+                 (Boolean'Pos (Val = 1 and Zx = 0), Boolean_Type);
+            end;
+
+         when Iir_Predefined_Ieee_Numeric_Std_Neg_Sgn =>
+            return Neg_Vec (Param1, +Expr);
+         when Iir_Predefined_Ieee_Numeric_Std_Abs_Sgn =>
+            return Abs_Vec (Param1, +Expr);
+
+         when Iir_Predefined_Ieee_1164_Vector_Not
+           | Iir_Predefined_Ieee_Numeric_Std_Not_Uns
+           | Iir_Predefined_Ieee_Numeric_Std_Not_Sgn =>
+            return Eval_Vector_Monadic (Param1, Not_Table);
+
+         when Iir_Predefined_Ieee_1164_Scalar_Not =>
+            return Create_Memory_U8
+              (Std_Ulogic'Pos (Not_Table (Read_Std_Logic (Param1.Mem, 0))),
+               Param1.Typ);
+
+         when Iir_Predefined_Ieee_1164_And_Suv
+            | Iir_Predefined_Ieee_Numeric_Std_And_Uns
+            | Iir_Predefined_Ieee_Numeric_Std_And_Sgn =>
+            return Eval_Vector_Reduce ('1', Param1, And_Table, False);
+         when Iir_Predefined_Ieee_1164_Nand_Suv
+            | Iir_Predefined_Ieee_Numeric_Std_Nand_Uns
+            | Iir_Predefined_Ieee_Numeric_Std_Nand_Sgn =>
+            return Eval_Vector_Reduce ('1', Param1, And_Table, True);
+
+         when Iir_Predefined_Ieee_1164_Or_Suv
+            | Iir_Predefined_Ieee_Numeric_Std_Or_Uns
+            | Iir_Predefined_Ieee_Numeric_Std_Or_Sgn =>
+            return Eval_Vector_Reduce ('0', Param1, Or_Table, False);
+         when Iir_Predefined_Ieee_1164_Nor_Suv
+            | Iir_Predefined_Ieee_Numeric_Std_Nor_Uns
+            | Iir_Predefined_Ieee_Numeric_Std_Nor_Sgn =>
+            return Eval_Vector_Reduce ('0', Param1, Or_Table, True);
+
+         when Iir_Predefined_Ieee_1164_Xor_Suv
+            | Iir_Predefined_Ieee_Numeric_Std_Xor_Uns
+            | Iir_Predefined_Ieee_Numeric_Std_Xor_Sgn =>
+            return Eval_Vector_Reduce ('0', Param1, Xor_Table, False);
+         when Iir_Predefined_Ieee_1164_Xnor_Suv
+            | Iir_Predefined_Ieee_Numeric_Std_Xnor_Uns
+            | Iir_Predefined_Ieee_Numeric_Std_Xnor_Sgn =>
+            return Eval_Vector_Reduce ('0', Param1, Xor_Table, True);
+
+         when Iir_Predefined_Ieee_Std_Logic_Arith_Id_Uns_Uns
+            | Iir_Predefined_Ieee_Std_Logic_Arith_Id_Uns_Slv
+            | Iir_Predefined_Ieee_Std_Logic_Arith_Id_Sgn_Sgn
+            | Iir_Predefined_Ieee_Std_Logic_Arith_Id_Sgn_Slv
+            | Iir_Predefined_Ieee_Std_Logic_Unsigned_Id_Slv
+            | Iir_Predefined_Ieee_Std_Logic_Signed_Id_Slv =>
+            return Param1;
+
+         when Iir_Predefined_Ieee_Std_Logic_Arith_Neg_Sgn_Sgn
+            | Iir_Predefined_Ieee_Std_Logic_Arith_Neg_Sgn_Slv
+            | Iir_Predefined_Ieee_Std_Logic_Signed_Neg_Slv =>
+            return Neg_Sgn_Sgn (Param1, +Expr);
+
+         when Iir_Predefined_Ieee_Std_Logic_Arith_Abs_Sgn_Sgn
+            | Iir_Predefined_Ieee_Std_Logic_Arith_Abs_Sgn_Slv
+            | Iir_Predefined_Ieee_Std_Logic_Signed_Abs_Slv =>
+            return Abs_Sgn_Sgn (Param1, +Expr);
+
          when Iir_Predefined_Boolean_Or
             | Iir_Predefined_Bit_Or
             | Iir_Predefined_Boolean_And
@@ -443,22 +1032,22 @@ package body Synth.Vhdl_Eval is
          when Iir_Predefined_Boolean_Xor
             | Iir_Predefined_Bit_Xor =>
             return Create_Memory_U8
-              (Boolean'Pos (Boolean'Val (Read_Discrete (Left))
-                              xor Boolean'Val (Read_Discrete (Right))),
+              (Boolean'Pos (Boolean'Val (Read_Discrete (Param1))
+                              xor Boolean'Val (Read_Discrete (Param2))),
                Res_Typ);
 
          when Iir_Predefined_Boolean_Nand
             | Iir_Predefined_Bit_Nand =>
             return Create_Memory_U8
-              (Boolean'Pos (not (Boolean'Val (Read_Discrete (Left))
-                                   and Boolean'Val (Read_Discrete (Right)))),
+              (Boolean'Pos (not (Boolean'Val (Read_Discrete (Param1))
+                                   and Boolean'Val (Read_Discrete (Param2)))),
                Res_Typ);
 
          when Iir_Predefined_Boolean_Nor
             | Iir_Predefined_Bit_Nor =>
             return Create_Memory_U8
-              (Boolean'Pos (not (Boolean'Val (Read_Discrete (Left))
-                                   or Boolean'Val (Read_Discrete (Right)))),
+              (Boolean'Pos (not (Boolean'Val (Read_Discrete (Param1))
+                                   or Boolean'Val (Read_Discrete (Param2)))),
                Res_Typ);
 
          when Iir_Predefined_Integer_Plus
@@ -466,7 +1055,7 @@ package body Synth.Vhdl_Eval is
             declare
                Res : Int64;
             begin
-               Res := Read_Discrete (Left) + Read_Discrete (Right);
+               Res := Read_Discrete (Param1) + Read_Discrete (Param2);
                Check_Integer_Overflow (Inst, Res, Res_Typ, Expr);
                return Create_Memory_Discrete (Res, Res_Typ);
             end;
@@ -475,7 +1064,7 @@ package body Synth.Vhdl_Eval is
             declare
                Res : Int64;
             begin
-               Res := Read_Discrete (Left) - Read_Discrete (Right);
+               Res := Read_Discrete (Param1) - Read_Discrete (Param2);
                Check_Integer_Overflow (Inst, Res, Res_Typ, Expr);
                return Create_Memory_Discrete (Res, Res_Typ);
             end;
@@ -485,7 +1074,7 @@ package body Synth.Vhdl_Eval is
             declare
                Res : Int64;
             begin
-               Res := Read_Discrete (Left) * Read_Discrete (Right);
+               Res := Read_Discrete (Param1) * Read_Discrete (Param2);
                Check_Integer_Overflow (Inst, Res, Res_Typ, Expr);
                return Create_Memory_Discrete (Res, Res_Typ);
             end;
@@ -496,12 +1085,12 @@ package body Synth.Vhdl_Eval is
                Rv : Int64;
                Res : Int64;
             begin
-               Rv := Read_Discrete (Right);
+               Rv := Read_Discrete (Param2);
                if Rv = 0 then
                   Error_Msg_Synth (Inst, Expr, "division by zero");
                   return Null_Memtyp;
                end if;
-               Res := Read_Discrete (Left) / Rv;
+               Res := Read_Discrete (Param1) / Rv;
                Check_Integer_Overflow (Inst, Res, Res_Typ, Expr);
                return Create_Memory_Discrete (Res, Res_Typ);
             end;
@@ -509,7 +1098,7 @@ package body Synth.Vhdl_Eval is
             declare
                Res : Int64;
             begin
-               Res := Read_Discrete (Left) mod Read_Discrete (Right);
+               Res := Read_Discrete (Param1) mod Read_Discrete (Param2);
                Check_Integer_Overflow (Inst, Res, Res_Typ, Expr);
                return Create_Memory_Discrete (Res, Res_Typ);
             end;
@@ -517,7 +1106,7 @@ package body Synth.Vhdl_Eval is
             declare
                Res : Int64;
             begin
-               Res := Read_Discrete (Left) rem Read_Discrete (Right);
+               Res := Read_Discrete (Param1) rem Read_Discrete (Param2);
                Check_Integer_Overflow (Inst, Res, Res_Typ, Expr);
                return Create_Memory_Discrete (Res, Res_Typ);
             end;
@@ -529,8 +1118,8 @@ package body Synth.Vhdl_Eval is
                Res : Ghdl_I64;
                Ovf : Boolean;
             begin
-               Lv := Ghdl_I64 (Read_Discrete (Left));
-               Rv := Std_Integer (Read_Discrete (Right));
+               Lv := Ghdl_I64 (Read_Discrete (Param1));
+               Rv := Std_Integer (Read_Discrete (Param2));
                Grt.Arith.Exp_I64 (Lv, Rv, Res, Ovf);
                if Ovf then
                   Error_Msg_Synth (Inst, Expr, "exponentiation overflow");
@@ -543,100 +1132,101 @@ package body Synth.Vhdl_Eval is
             | Iir_Predefined_Physical_Less_Equal
             | Iir_Predefined_Enum_Less_Equal =>
             return Create_Memory_Boolean
-              (Read_Discrete (Left) <= Read_Discrete (Right));
+              (Read_Discrete (Param1) <= Read_Discrete (Param2));
          when Iir_Predefined_Integer_Less
             | Iir_Predefined_Physical_Less
             | Iir_Predefined_Enum_Less =>
             return Create_Memory_Boolean
-              (Read_Discrete (Left) < Read_Discrete (Right));
+              (Read_Discrete (Param1) < Read_Discrete (Param2));
          when Iir_Predefined_Integer_Greater_Equal
             | Iir_Predefined_Physical_Greater_Equal
             | Iir_Predefined_Enum_Greater_Equal =>
             return Create_Memory_Boolean
-              (Read_Discrete (Left) >= Read_Discrete (Right));
+              (Read_Discrete (Param1) >= Read_Discrete (Param2));
          when Iir_Predefined_Integer_Greater
             | Iir_Predefined_Physical_Greater
             | Iir_Predefined_Enum_Greater =>
             return Create_Memory_Boolean
-              (Read_Discrete (Left) > Read_Discrete (Right));
+              (Read_Discrete (Param1) > Read_Discrete (Param2));
          when Iir_Predefined_Integer_Equality
             | Iir_Predefined_Physical_Equality
             | Iir_Predefined_Enum_Equality
             | Iir_Predefined_Bit_Match_Equality =>
             return Create_Memory_Boolean
-              (Read_Discrete (Left) = Read_Discrete (Right));
+              (Read_Discrete (Param1) = Read_Discrete (Param2));
          when Iir_Predefined_Integer_Inequality
             | Iir_Predefined_Physical_Inequality
             | Iir_Predefined_Enum_Inequality
             | Iir_Predefined_Bit_Match_Inequality =>
             return Create_Memory_Boolean
-              (Read_Discrete (Left) /= Read_Discrete (Right));
+              (Read_Discrete (Param1) /= Read_Discrete (Param2));
 
          when Iir_Predefined_Physical_Real_Mul =>
             return Create_Memory_Discrete
-              (Int64 (Fp64 (Read_Discrete (Left)) * Read_Fp64 (Right)),
+              (Int64 (Fp64 (Read_Discrete (Param1)) * Read_Fp64 (Param2)),
                Res_Typ);
          when Iir_Predefined_Real_Physical_Mul =>
             return Create_Memory_Discrete
-              (Int64 (Read_Fp64 (Left) * Fp64 (Read_Discrete (Right))),
+              (Int64 (Read_Fp64 (Param1) * Fp64 (Read_Discrete (Param2))),
                Res_Typ);
          when Iir_Predefined_Physical_Real_Div =>
             return Create_Memory_Discrete
-              (Int64 (Fp64 (Read_Discrete (Left)) / Read_Fp64 (Right)),
+              (Int64 (Fp64 (Read_Discrete (Param1)) / Read_Fp64 (Param2)),
                Res_Typ);
 
          when Iir_Predefined_Floating_Less =>
             return Create_Memory_U8
-              (Boolean'Pos (Read_Fp64 (Left) < Read_Fp64 (Right)),
+              (Boolean'Pos (Read_Fp64 (Param1) < Read_Fp64 (Param2)),
                Boolean_Type);
          when Iir_Predefined_Floating_Less_Equal =>
             return Create_Memory_U8
-              (Boolean'Pos (Read_Fp64 (Left) <= Read_Fp64 (Right)),
+              (Boolean'Pos (Read_Fp64 (Param1) <= Read_Fp64 (Param2)),
                Boolean_Type);
          when Iir_Predefined_Floating_Equality =>
             return Create_Memory_U8
-              (Boolean'Pos (Read_Fp64 (Left) = Read_Fp64 (Right)),
+              (Boolean'Pos (Read_Fp64 (Param1) = Read_Fp64 (Param2)),
                Boolean_Type);
          when Iir_Predefined_Floating_Inequality =>
             return Create_Memory_U8
-              (Boolean'Pos (Read_Fp64 (Left) /= Read_Fp64 (Right)),
+              (Boolean'Pos (Read_Fp64 (Param1) /= Read_Fp64 (Param2)),
                Boolean_Type);
          when Iir_Predefined_Floating_Greater =>
             return Create_Memory_U8
-              (Boolean'Pos (Read_Fp64 (Left) > Read_Fp64 (Right)),
+              (Boolean'Pos (Read_Fp64 (Param1) > Read_Fp64 (Param2)),
                Boolean_Type);
          when Iir_Predefined_Floating_Greater_Equal =>
             return Create_Memory_U8
-              (Boolean'Pos (Read_Fp64 (Left) >= Read_Fp64 (Right)),
+              (Boolean'Pos (Read_Fp64 (Param1) >= Read_Fp64 (Param2)),
                Boolean_Type);
 
          when Iir_Predefined_Floating_Plus =>
-            return Create_Memory_Fp64 (Read_Fp64 (Left) + Read_Fp64 (Right),
+            return Create_Memory_Fp64 (Read_Fp64 (Param1) + Read_Fp64 (Param2),
                                        Res_Typ);
          when Iir_Predefined_Floating_Minus =>
-            return Create_Memory_Fp64 (Read_Fp64 (Left) - Read_Fp64 (Right),
+            return Create_Memory_Fp64 (Read_Fp64 (Param1) - Read_Fp64 (Param2),
                                        Res_Typ);
          when Iir_Predefined_Floating_Mul =>
-            return Create_Memory_Fp64 (Read_Fp64 (Left) * Read_Fp64 (Right),
+            return Create_Memory_Fp64 (Read_Fp64 (Param1) * Read_Fp64 (Param2),
                                        Res_Typ);
          when Iir_Predefined_Floating_Div =>
-            return Create_Memory_Fp64 (Read_Fp64 (Left) / Read_Fp64 (Right),
+            return Create_Memory_Fp64 (Read_Fp64 (Param1) / Read_Fp64 (Param2),
                                        Res_Typ);
          when Iir_Predefined_Floating_Exp =>
             return Create_Memory_Fp64
-              (Read_Fp64 (Left) ** Integer (Read_Discrete (Right)), Res_Typ);
+              (Read_Fp64 (Param1)
+                 ** Integer (Read_Discrete (Param2)), Res_Typ);
 
          when Iir_Predefined_Universal_R_I_Div =>
             declare
                Rv : Int64;
                Res : Fp64;
             begin
-               Rv := Read_Discrete (Right);
+               Rv := Read_Discrete (Param2);
                if Rv = 0 then
                   Error_Msg_Synth (Inst, Expr, "division by zero");
                   return Null_Memtyp;
                end if;
-               Res := Read_Fp64 (Left) / Fp64 (Rv);
+               Res := Read_Fp64 (Param1) / Fp64 (Rv);
                return Create_Memory_Fp64 (Res, Res_Typ);
             end;
 
@@ -644,11 +1234,11 @@ package body Synth.Vhdl_Eval is
             declare
                use Flags;
                L_Len : constant Iir_Index32 :=
-                 Iir_Index32 (Get_Bound_Length (Left.Typ));
+                 Iir_Index32 (Get_Bound_Length (Param1.Typ));
                R_Len : constant Iir_Index32 :=
-                 Iir_Index32 (Get_Bound_Length (Right.Typ));
-               Le_Typ : constant Type_Acc := Get_Array_Element (Left.Typ);
-               Re_Typ : constant Type_Acc := Get_Array_Element (Right.Typ);
+                 Iir_Index32 (Get_Bound_Length (Param2.Typ));
+               Le_Typ : constant Type_Acc := Get_Array_Element (Param1.Typ);
+               Re_Typ : constant Type_Acc := Get_Array_Element (Param2.Typ);
                El_Typ : Type_Acc;
                Bnd : Bound_Type;
                Res_St : Type_Acc;
@@ -659,7 +1249,7 @@ package body Synth.Vhdl_Eval is
                   --  LRM08 9.2.5 Adding operators
                   --  If both operands are null arrays, then the result of the
                   --  concatenation is the right operand.
-                  return Right;
+                  return Param2;
                end if;
                if Vhdl_Std > Vhdl_87 then
                   Bnd := Elab.Vhdl_Types.Create_Bounds_From_Length
@@ -670,7 +1260,7 @@ package body Synth.Vhdl_Eval is
                   --  case the result of the concatenation is the right
                   --  operand.
                   if L_Len = 0 then
-                     return Right;
+                     return Param2;
                   end if;
 
                   --  LRM87 7.2.3
@@ -679,8 +1269,8 @@ package body Synth.Vhdl_Eval is
                   --  LRM87 7.2.3
                   --  The direction of the result is the direction of the left
                   --  operand, [...]
-                  Bnd.Left := Left.Typ.Abound.Left;
-                  Bnd.Dir := Left.Typ.Abound.Dir;
+                  Bnd.Left := Param1.Typ.Abound.Left;
+                  Bnd.Dir := Param1.Typ.Abound.Dir;
                   Bnd.Len := Uns32 (L_Len + R_Len);
                   --  TODO: overflow.
                   case Bnd.Dir is
@@ -695,25 +1285,26 @@ package body Synth.Vhdl_Eval is
                Res_St := Create_Onedimensional_Array_Subtype
                  (Res_Typ, Bnd, El_Typ);
                Res := Create_Memory (Res_St);
-               if Left.Typ.Sz > 0 then
-                  Copy_Memory (Res.Mem, Left.Mem, Left.Typ.Sz);
+               if Param1.Typ.Sz > 0 then
+                  Copy_Memory (Res.Mem, Param1.Mem, Param1.Typ.Sz);
                end if;
-               if Right.Typ.Sz > 0 then
-                  Copy_Memory (Res.Mem + Left.Typ.Sz, Right.Mem, Right.Typ.Sz);
+               if Param2.Typ.Sz > 0 then
+                  Copy_Memory
+                    (Res.Mem + Param1.Typ.Sz, Param2.Mem, Param2.Typ.Sz);
                end if;
                return Res;
             end;
          when Iir_Predefined_Element_Array_Concat =>
             declare
                Rlen : constant Iir_Index32 :=
-                 Iir_Index32 (Get_Bound_Length (Right.Typ));
-               Re_Typ : constant Type_Acc := Get_Array_Element (Right.Typ);
+                 Iir_Index32 (Get_Bound_Length (Param2.Typ));
+               Re_Typ : constant Type_Acc := Get_Array_Element (Param2.Typ);
                El_Typ : Type_Acc;
                Bnd : Bound_Type;
                Res_St : Type_Acc;
                Res : Memtyp;
             begin
-               Check_Matching_Bounds (Left.Typ, Re_Typ, Expr);
+               Check_Matching_Bounds (Param1.Typ, Re_Typ, Expr);
                Bnd := Elab.Vhdl_Types.Create_Bounds_From_Length
                  (Get_Uarray_Index (Res_Typ).Drange, 1 + Rlen);
                El_Typ := Unshare_Type_Expr (Re_Typ,
@@ -721,22 +1312,22 @@ package body Synth.Vhdl_Eval is
                Res_St := Create_Onedimensional_Array_Subtype
                  (Res_Typ, Bnd, El_Typ);
                Res := Create_Memory (Res_St);
-               Copy_Memory (Res.Mem, Left.Mem, Left.Typ.Sz);
-               Copy_Memory (Res.Mem + Left.Typ.Sz,
-                            Right.Mem, Right.Typ.Sz);
+               Copy_Memory (Res.Mem, Param1.Mem, Param1.Typ.Sz);
+               Copy_Memory (Res.Mem + Param1.Typ.Sz,
+                            Param2.Mem, Param2.Typ.Sz);
                return Res;
             end;
          when Iir_Predefined_Array_Element_Concat =>
             declare
                Llen : constant Iir_Index32 :=
-                 Iir_Index32 (Get_Bound_Length (Left.Typ));
-               Le_Typ : constant Type_Acc := Get_Array_Element (Left.Typ);
+                 Iir_Index32 (Get_Bound_Length (Param1.Typ));
+               Le_Typ : constant Type_Acc := Get_Array_Element (Param1.Typ);
                El_Typ : Type_Acc;
                Bnd : Bound_Type;
                Res_St : Type_Acc;
                Res : Memtyp;
             begin
-               Check_Matching_Bounds (Le_Typ, Right.Typ, Expr);
+               Check_Matching_Bounds (Le_Typ, Param2.Typ, Expr);
                Bnd := Elab.Vhdl_Types.Create_Bounds_From_Length
                  (Get_Uarray_Index (Res_Typ).Drange, Llen + 1);
                El_Typ := Unshare_Type_Expr (Le_Typ,
@@ -744,20 +1335,20 @@ package body Synth.Vhdl_Eval is
                Res_St := Create_Onedimensional_Array_Subtype
                  (Res_Typ, Bnd, El_Typ);
                Res := Create_Memory (Res_St);
-               Copy_Memory (Res.Mem, Left.Mem, Left.Typ.Sz);
-               Copy_Memory (Res.Mem + Left.Typ.Sz,
-                            Right.Mem, Right.Typ.Sz);
+               Copy_Memory (Res.Mem, Param1.Mem, Param1.Typ.Sz);
+               Copy_Memory (Res.Mem + Param1.Typ.Sz,
+                            Param2.Mem, Param2.Typ.Sz);
                return Res;
             end;
          when Iir_Predefined_Element_Element_Concat =>
             declare
-               Le_Typ : constant Type_Acc := Left.Typ;
+               Le_Typ : constant Type_Acc := Param1.Typ;
                El_Typ : Type_Acc;
                Bnd : Bound_Type;
                Res_St : Type_Acc;
                Res : Memtyp;
             begin
-               Check_Matching_Bounds (Left.Typ, Right.Typ, Expr);
+               Check_Matching_Bounds (Param1.Typ, Param2.Typ, Expr);
                Bnd := Elab.Vhdl_Types.Create_Bounds_From_Length
                  (Get_Uarray_Index (Res_Typ).Drange, 2);
                El_Typ := Unshare_Type_Expr (Le_Typ,
@@ -765,54 +1356,54 @@ package body Synth.Vhdl_Eval is
                Res_St := Create_Onedimensional_Array_Subtype
                  (Res_Typ, Bnd, El_Typ);
                Res := Create_Memory (Res_St);
-               Copy_Memory (Res.Mem, Left.Mem, El_Typ.Sz);
+               Copy_Memory (Res.Mem, Param1.Mem, El_Typ.Sz);
                Copy_Memory (Res.Mem + El_Typ.Sz,
-                            Right.Mem, El_Typ.Sz);
+                            Param2.Mem, El_Typ.Sz);
                return Res;
             end;
 
          when Iir_Predefined_Array_Equality
             | Iir_Predefined_Record_Equality
             | Iir_Predefined_Bit_Array_Match_Equality =>
-            return Create_Memory_Boolean (Is_Equal (Left, Right));
+            return Create_Memory_Boolean (Is_Equal (Param1, Param2));
          when Iir_Predefined_Array_Inequality
             | Iir_Predefined_Record_Inequality
             | Iir_Predefined_Bit_Array_Match_Inequality =>
-            return Create_Memory_Boolean (not Is_Equal (Left, Right));
+            return Create_Memory_Boolean (not Is_Equal (Param1, Param2));
 
          when Iir_Predefined_Access_Equality =>
             return Create_Memory_Boolean
-              (Read_Access (Left) = Read_Access (Right));
+              (Read_Access (Param1) = Read_Access (Param2));
          when Iir_Predefined_Access_Inequality =>
             return Create_Memory_Boolean
-              (Read_Access (Left) /= Read_Access (Right));
+              (Read_Access (Param1) /= Read_Access (Param2));
 
          when Iir_Predefined_Array_Less =>
             return Create_Memory_Boolean
-              (Compare_Array (Left, Right) = Less);
+              (Compare_Array (Param1, Param2) = Less);
          when Iir_Predefined_Array_Less_Equal =>
             return Create_Memory_Boolean
-              (Compare_Array (Left, Right) <= Equal);
+              (Compare_Array (Param1, Param2) <= Equal);
          when Iir_Predefined_Array_Greater =>
             return Create_Memory_Boolean
-              (Compare_Array (Left, Right) = Greater);
+              (Compare_Array (Param1, Param2) = Greater);
          when Iir_Predefined_Array_Greater_Equal =>
             return Create_Memory_Boolean
-              (Compare_Array (Left, Right) >= Equal);
+              (Compare_Array (Param1, Param2) >= Equal);
 
          when Iir_Predefined_Array_Maximum =>
             --  IEEE 1076-2008 5.3.2.4 Predefined operations on array types
-            if Compare_Array (Left, Right) = Less then
-               return Right;
+            if Compare_Array (Param1, Param2) = Less then
+               return Param2;
             else
-               return Left;
+               return Param1;
             end if;
          when Iir_Predefined_Array_Minimum =>
             --  IEEE 1076-2008 5.3.2.4 Predefined operations on array types
-            if Compare_Array (Left, Right) = Less then
-               return Left;
+            if Compare_Array (Param1, Param2) = Less then
+               return Param1;
             else
-               return Right;
+               return Param2;
             end if;
 
          when Iir_Predefined_Array_Sll
@@ -820,182 +1411,189 @@ package body Synth.Vhdl_Eval is
            | Iir_Predefined_Array_Rol
            | Iir_Predefined_Array_Ror =>
             return Execute_Shift_Operator
-              (Left, Read_Discrete (Right), 0, Def);
+              (Param1, Read_Discrete (Param2), 0, Def);
 
          when Iir_Predefined_TF_Array_And =>
-            return Eval_TF_Vector_Dyadic (Inst, Left, Right, Tf_2d_And, Expr);
+            return Eval_TF_Vector_Dyadic
+              (Inst, Param1, Param2, Tf_2d_And, Expr);
          when Iir_Predefined_TF_Array_Or =>
-            return Eval_TF_Vector_Dyadic (Inst, Left, Right, Tf_2d_Or, Expr);
+            return Eval_TF_Vector_Dyadic
+              (Inst, Param1, Param2, Tf_2d_Or, Expr);
          when Iir_Predefined_TF_Array_Xor =>
-            return Eval_TF_Vector_Dyadic (Inst, Left, Right, Tf_2d_Xor, Expr);
+            return Eval_TF_Vector_Dyadic
+              (Inst, Param1, Param2, Tf_2d_Xor, Expr);
          when Iir_Predefined_TF_Array_Nand =>
-            return Eval_TF_Vector_Dyadic (Inst, Left, Right, Tf_2d_Nand, Expr);
+            return Eval_TF_Vector_Dyadic
+              (Inst, Param1, Param2, Tf_2d_Nand, Expr);
          when Iir_Predefined_TF_Array_Nor =>
-            return Eval_TF_Vector_Dyadic (Inst, Left, Right, Tf_2d_Nor, Expr);
+            return Eval_TF_Vector_Dyadic
+              (Inst, Param1, Param2, Tf_2d_Nor, Expr);
          when Iir_Predefined_TF_Array_Xnor =>
-            return Eval_TF_Vector_Dyadic (Inst, Left, Right, Tf_2d_Xnor, Expr);
+            return Eval_TF_Vector_Dyadic
+              (Inst, Param1, Param2, Tf_2d_Xnor, Expr);
 
          when Iir_Predefined_TF_Element_Array_Or =>
-            return Eval_TF_Array_Element (Left, Right, Tf_2d_Or);
+            return Eval_TF_Array_Element (Param1, Param2, Tf_2d_Or);
          when Iir_Predefined_TF_Array_Element_Or =>
-            return Eval_TF_Array_Element (Right, Left, Tf_2d_Or);
+            return Eval_TF_Array_Element (Param2, Param1, Tf_2d_Or);
 
          when Iir_Predefined_TF_Element_Array_Nor =>
-            return Eval_TF_Array_Element (Left, Right, Tf_2d_Nor);
+            return Eval_TF_Array_Element (Param1, Param2, Tf_2d_Nor);
          when Iir_Predefined_TF_Array_Element_Nor =>
-            return Eval_TF_Array_Element (Right, Left, Tf_2d_Nor);
+            return Eval_TF_Array_Element (Param2, Param1, Tf_2d_Nor);
 
          when Iir_Predefined_TF_Element_Array_And =>
-            return Eval_TF_Array_Element (Left, Right, Tf_2d_And);
+            return Eval_TF_Array_Element (Param1, Param2, Tf_2d_And);
          when Iir_Predefined_TF_Array_Element_And =>
-            return Eval_TF_Array_Element (Right, Left, Tf_2d_And);
+            return Eval_TF_Array_Element (Param2, Param1, Tf_2d_And);
 
          when Iir_Predefined_TF_Element_Array_Nand =>
-            return Eval_TF_Array_Element (Left, Right, Tf_2d_Nand);
+            return Eval_TF_Array_Element (Param1, Param2, Tf_2d_Nand);
          when Iir_Predefined_TF_Array_Element_Nand =>
-            return Eval_TF_Array_Element (Right, Left, Tf_2d_Nand);
+            return Eval_TF_Array_Element (Param2, Param1, Tf_2d_Nand);
 
          when Iir_Predefined_TF_Element_Array_Xor =>
-            return Eval_TF_Array_Element (Left, Right, Tf_2d_Xor);
+            return Eval_TF_Array_Element (Param1, Param2, Tf_2d_Xor);
          when Iir_Predefined_TF_Array_Element_Xor =>
-            return Eval_TF_Array_Element (Right, Left, Tf_2d_Xor);
+            return Eval_TF_Array_Element (Param2, Param1, Tf_2d_Xor);
 
          when Iir_Predefined_TF_Element_Array_Xnor =>
-            return Eval_TF_Array_Element (Left, Right, Tf_2d_Xnor);
+            return Eval_TF_Array_Element (Param1, Param2, Tf_2d_Xnor);
          when Iir_Predefined_TF_Array_Element_Xnor =>
-            return Eval_TF_Array_Element (Right, Left, Tf_2d_Xnor);
+            return Eval_TF_Array_Element (Param2, Param1, Tf_2d_Xnor);
 
          when Iir_Predefined_Ieee_1164_Vector_And
            | Iir_Predefined_Ieee_Numeric_Std_And_Uns_Uns
            | Iir_Predefined_Ieee_Numeric_Std_And_Sgn_Sgn =>
-            return Eval_Vector_Dyadic (Inst, Left, Right, And_Table, Expr);
+            return Eval_Vector_Dyadic (Inst, Param1, Param2, And_Table, Expr);
 
          when Iir_Predefined_Ieee_1164_Vector_Nand
            | Iir_Predefined_Ieee_Numeric_Std_Nand_Uns_Uns
            | Iir_Predefined_Ieee_Numeric_Std_Nand_Sgn_Sgn =>
-            return Eval_Vector_Dyadic (Inst, Left, Right, Nand_Table, Expr);
+            return Eval_Vector_Dyadic (Inst, Param1, Param2, Nand_Table, Expr);
 
          when Iir_Predefined_Ieee_1164_Vector_Or
            | Iir_Predefined_Ieee_Numeric_Std_Or_Uns_Uns
            | Iir_Predefined_Ieee_Numeric_Std_Or_Sgn_Sgn =>
-            return Eval_Vector_Dyadic (Inst, Left, Right, Or_Table, Expr);
+            return Eval_Vector_Dyadic (Inst, Param1, Param2, Or_Table, Expr);
 
          when Iir_Predefined_Ieee_1164_Vector_Nor
            | Iir_Predefined_Ieee_Numeric_Std_Nor_Uns_Uns
            | Iir_Predefined_Ieee_Numeric_Std_Nor_Sgn_Sgn =>
-            return Eval_Vector_Dyadic (Inst, Left, Right, Nor_Table, Expr);
+            return Eval_Vector_Dyadic (Inst, Param1, Param2, Nor_Table, Expr);
 
          when Iir_Predefined_Ieee_1164_Vector_Xor
            | Iir_Predefined_Ieee_Numeric_Std_Xor_Uns_Uns
            | Iir_Predefined_Ieee_Numeric_Std_Xor_Sgn_Sgn =>
-            return Eval_Vector_Dyadic (Inst, Left, Right, Xor_Table, Expr);
+            return Eval_Vector_Dyadic (Inst, Param1, Param2, Xor_Table, Expr);
 
          when Iir_Predefined_Ieee_1164_Vector_Xnor
             | Iir_Predefined_Ieee_Numeric_Std_Xnor_Uns_Uns
             | Iir_Predefined_Ieee_Numeric_Std_Xnor_Sgn_Sgn =>
-            return Eval_Vector_Dyadic (Inst, Left, Right, Xnor_Table, Expr);
+            return Eval_Vector_Dyadic (Inst, Param1, Param2, Xnor_Table, Expr);
 
          when Iir_Predefined_Ieee_1164_Scalar_And =>
-            return Eval_Logic_Scalar (Left, Right, And_Table);
+            return Eval_Logic_Scalar (Param1, Param2, And_Table);
          when Iir_Predefined_Ieee_1164_Scalar_Or =>
-            return Eval_Logic_Scalar (Left, Right, Or_Table);
+            return Eval_Logic_Scalar (Param1, Param2, Or_Table);
          when Iir_Predefined_Ieee_1164_Scalar_Xor =>
-            return Eval_Logic_Scalar (Left, Right, Xor_Table);
+            return Eval_Logic_Scalar (Param1, Param2, Xor_Table);
          when Iir_Predefined_Ieee_1164_Scalar_Nand =>
-            return Eval_Logic_Scalar (Left, Right, Nand_Table);
+            return Eval_Logic_Scalar (Param1, Param2, Nand_Table);
          when Iir_Predefined_Ieee_1164_Scalar_Nor =>
-            return Eval_Logic_Scalar (Left, Right, Nor_Table);
+            return Eval_Logic_Scalar (Param1, Param2, Nor_Table);
          when Iir_Predefined_Ieee_1164_Scalar_Xnor =>
-            return Eval_Logic_Scalar (Left, Right, Xnor_Table);
+            return Eval_Logic_Scalar (Param1, Param2, Xnor_Table);
 
          when Iir_Predefined_Std_Ulogic_Match_Equality =>
-            return Eval_Logic_Scalar (Left, Right, Match_Eq_Table);
+            return Eval_Logic_Scalar (Param1, Param2, Match_Eq_Table);
          when Iir_Predefined_Std_Ulogic_Match_Inequality =>
-            return Eval_Logic_Scalar (Left, Right, Match_Eq_Table, True);
+            return Eval_Logic_Scalar (Param1, Param2, Match_Eq_Table, True);
          when Iir_Predefined_Std_Ulogic_Match_Greater =>
-            return Eval_Logic_Scalar (Left, Right, Match_Gt_Table);
+            return Eval_Logic_Scalar (Param1, Param2, Match_Gt_Table);
          when Iir_Predefined_Std_Ulogic_Match_Greater_Equal =>
-            return Eval_Logic_Scalar (Left, Right, Match_Ge_Table);
+            return Eval_Logic_Scalar (Param1, Param2, Match_Ge_Table);
          when Iir_Predefined_Std_Ulogic_Match_Less_Equal =>
-            return Eval_Logic_Scalar (Left, Right, Match_Le_Table);
+            return Eval_Logic_Scalar (Param1, Param2, Match_Le_Table);
          when Iir_Predefined_Std_Ulogic_Match_Less =>
-            return Eval_Logic_Scalar (Left, Right, Match_Lt_Table);
+            return Eval_Logic_Scalar (Param1, Param2, Match_Lt_Table);
 
          when Iir_Predefined_Std_Ulogic_Array_Match_Equality =>
-            return Eval_Vector_Match (Inst, Left, Right, False, Expr);
+            return Eval_Vector_Match (Inst, Param1, Param2, False, Expr);
          when Iir_Predefined_Std_Ulogic_Array_Match_Inequality =>
-            return Eval_Vector_Match (Inst, Left, Right, True, Expr);
+            return Eval_Vector_Match (Inst, Param1, Param2, True, Expr);
 
          when Iir_Predefined_Ieee_1164_And_Suv_Log
             | Iir_Predefined_Ieee_Numeric_Std_And_Uns_Log
             | Iir_Predefined_Ieee_Numeric_Std_And_Sgn_Log =>
-            return Eval_Logic_Vector_Scalar (Left, Right, And_Table);
+            return Eval_Logic_Vector_Scalar (Param1, Param2, And_Table);
          when Iir_Predefined_Ieee_1164_Or_Suv_Log
             | Iir_Predefined_Ieee_Numeric_Std_Or_Uns_Log
             | Iir_Predefined_Ieee_Numeric_Std_Or_Sgn_Log =>
-            return Eval_Logic_Vector_Scalar (Left, Right, Or_Table);
+            return Eval_Logic_Vector_Scalar (Param1, Param2, Or_Table);
          when Iir_Predefined_Ieee_1164_Xor_Suv_Log
             | Iir_Predefined_Ieee_Numeric_Std_Xor_Uns_Log
             | Iir_Predefined_Ieee_Numeric_Std_Xor_Sgn_Log =>
-            return Eval_Logic_Vector_Scalar (Left, Right, Xor_Table);
+            return Eval_Logic_Vector_Scalar (Param1, Param2, Xor_Table);
          when Iir_Predefined_Ieee_1164_Nand_Suv_Log
             | Iir_Predefined_Ieee_Numeric_Std_Nand_Uns_Log
             | Iir_Predefined_Ieee_Numeric_Std_Nand_Sgn_Log =>
-            return Eval_Logic_Vector_Scalar (Left, Right, Nand_Table);
+            return Eval_Logic_Vector_Scalar (Param1, Param2, Nand_Table);
          when Iir_Predefined_Ieee_1164_Nor_Suv_Log
             | Iir_Predefined_Ieee_Numeric_Std_Nor_Uns_Log
             | Iir_Predefined_Ieee_Numeric_Std_Nor_Sgn_Log =>
-            return Eval_Logic_Vector_Scalar (Left, Right, Nor_Table);
+            return Eval_Logic_Vector_Scalar (Param1, Param2, Nor_Table);
          when Iir_Predefined_Ieee_1164_Xnor_Suv_Log
             | Iir_Predefined_Ieee_Numeric_Std_Xnor_Uns_Log
             | Iir_Predefined_Ieee_Numeric_Std_Xnor_Sgn_Log =>
-            return Eval_Logic_Vector_Scalar (Left, Right, Xnor_Table);
+            return Eval_Logic_Vector_Scalar (Param1, Param2, Xnor_Table);
 
          when Iir_Predefined_Ieee_1164_And_Log_Suv
            | Iir_Predefined_Ieee_Numeric_Std_And_Log_Uns
            | Iir_Predefined_Ieee_Numeric_Std_And_Log_Sgn =>
-            return Eval_Logic_Vector_Scalar (Right, Left, And_Table);
+            return Eval_Logic_Vector_Scalar (Param2, Param1, And_Table);
          when Iir_Predefined_Ieee_1164_Or_Log_Suv
            | Iir_Predefined_Ieee_Numeric_Std_Or_Log_Uns
            | Iir_Predefined_Ieee_Numeric_Std_Or_Log_Sgn =>
-            return Eval_Logic_Vector_Scalar (Right, Left, Or_Table);
+            return Eval_Logic_Vector_Scalar (Param2, Param1, Or_Table);
          when Iir_Predefined_Ieee_1164_Xor_Log_Suv
            | Iir_Predefined_Ieee_Numeric_Std_Xor_Log_Uns
            | Iir_Predefined_Ieee_Numeric_Std_Xor_Log_Sgn =>
-            return Eval_Logic_Vector_Scalar (Right, Left, Xor_Table);
+            return Eval_Logic_Vector_Scalar (Param2, Param1, Xor_Table);
          when Iir_Predefined_Ieee_1164_Nand_Log_Suv
            | Iir_Predefined_Ieee_Numeric_Std_Nand_Log_Uns
            | Iir_Predefined_Ieee_Numeric_Std_Nand_Log_Sgn =>
-            return Eval_Logic_Vector_Scalar (Right, Left, Nand_Table);
+            return Eval_Logic_Vector_Scalar (Param2, Param1, Nand_Table);
          when Iir_Predefined_Ieee_1164_Nor_Log_Suv
            | Iir_Predefined_Ieee_Numeric_Std_Nor_Log_Uns
            | Iir_Predefined_Ieee_Numeric_Std_Nor_Log_Sgn =>
-            return Eval_Logic_Vector_Scalar (Right, Left, Nor_Table);
+            return Eval_Logic_Vector_Scalar (Param2, Param1, Nor_Table);
          when Iir_Predefined_Ieee_1164_Xnor_Log_Suv
            | Iir_Predefined_Ieee_Numeric_Std_Xnor_Log_Uns
            | Iir_Predefined_Ieee_Numeric_Std_Xnor_Log_Sgn =>
-            return Eval_Logic_Vector_Scalar (Right, Left, Xnor_Table);
+            return Eval_Logic_Vector_Scalar (Param2, Param1, Xnor_Table);
 
          when Iir_Predefined_Ieee_1164_Vector_Sll
             | Iir_Predefined_Ieee_Numeric_Std_Sla_Uns_Int =>
             return Execute_Shift_Operator
-              (Left, Read_Discrete (Right), Std_Ulogic'Pos('0'),
+              (Param1, Read_Discrete (Param2), Std_Ulogic'Pos('0'),
                Iir_Predefined_Array_Sll);
          when Iir_Predefined_Ieee_1164_Vector_Srl
             | Iir_Predefined_Ieee_Numeric_Std_Sra_Uns_Int =>
             return Execute_Shift_Operator
-              (Left, Read_Discrete (Right), Std_Ulogic'Pos('0'),
+              (Param1, Read_Discrete (Param2), Std_Ulogic'Pos('0'),
                Iir_Predefined_Array_Srl);
          when Iir_Predefined_Ieee_Numeric_Std_Sra_Sgn_Int =>
             declare
-               Cnt : constant Int64 := Read_Discrete (Right);
+               Cnt : constant Int64 := Read_Discrete (Param2);
             begin
                if Cnt >= 0 then
                   return Execute_Shift_Operator
-                    (Left, Cnt, Std_Ulogic'Pos('0'), Iir_Predefined_Array_Sra);
+                    (Param1, Cnt, Std_Ulogic'Pos('0'),
+                     Iir_Predefined_Array_Sra);
                else
                   return Execute_Shift_Operator
-                    (Left, -Cnt, Std_Ulogic'Pos('0'),
+                    (Param1, -Cnt, Std_Ulogic'Pos('0'),
                      Iir_Predefined_Array_Sll);
                end if;
             end;
@@ -1004,7 +1602,7 @@ package body Synth.Vhdl_Eval is
                Cnt : Int64;
                Op : Iir_Predefined_Shift_Functions;
             begin
-               Cnt := Read_Discrete (Right);
+               Cnt := Read_Discrete (Param2);
                if Cnt >= 0 then
                   Op := Iir_Predefined_Array_Sll;
                else
@@ -1012,20 +1610,20 @@ package body Synth.Vhdl_Eval is
                   Op :=Iir_Predefined_Array_Sra;
                end if;
                return Execute_Shift_Operator
-                 (Left, Cnt, Std_Ulogic'Pos('0'), Op);
+                 (Param1, Cnt, Std_Ulogic'Pos('0'), Op);
             end;
 
          when Iir_Predefined_Ieee_1164_Vector_Rol
             | Iir_Predefined_Ieee_Numeric_Std_Rol_Uns_Int
             | Iir_Predefined_Ieee_Numeric_Std_Rol_Sgn_Int =>
             return Execute_Shift_Operator
-              (Left, Read_Discrete (Right), Std_Ulogic'Pos('0'),
+              (Param1, Read_Discrete (Param2), Std_Ulogic'Pos('0'),
                Iir_Predefined_Array_Rol);
          when Iir_Predefined_Ieee_1164_Vector_Ror
             | Iir_Predefined_Ieee_Numeric_Std_Ror_Uns_Int
             | Iir_Predefined_Ieee_Numeric_Std_Ror_Sgn_Int =>
             return Execute_Shift_Operator
-              (Left, Read_Discrete (Right), Std_Ulogic'Pos('0'),
+              (Param1, Read_Discrete (Param2), Std_Ulogic'Pos('0'),
                Iir_Predefined_Array_Ror);
 
          when Iir_Predefined_Ieee_Numeric_Std_Eq_Uns_Uns
@@ -1034,21 +1632,21 @@ package body Synth.Vhdl_Eval is
             declare
                Res : Boolean;
             begin
-               Res := Compare_Uns_Uns (Left, Right, Greater, +Expr) = Equal;
+               Res := Compare_Uns_Uns (Param1, Param2, Greater, +Expr) = Equal;
                return Create_Memory_Boolean (Res);
             end;
          when Iir_Predefined_Ieee_Numeric_Std_Eq_Uns_Nat =>
             declare
                Res : Boolean;
             begin
-               Res := Compare_Uns_Nat (Left, Right, Greater, +Expr) = Equal;
+               Res := Compare_Uns_Nat (Param1, Param2, Greater, +Expr) = Equal;
                return Create_Memory_Boolean (Res);
             end;
          when Iir_Predefined_Ieee_Numeric_Std_Eq_Nat_Uns =>
             declare
                Res : Boolean;
             begin
-               Res := Compare_Uns_Nat (Right, Left, Greater, +Expr) = Equal;
+               Res := Compare_Uns_Nat (Param2, Param1, Greater, +Expr) = Equal;
                return Create_Memory_Boolean (Res);
             end;
          when Iir_Predefined_Ieee_Numeric_Std_Eq_Sgn_Sgn
@@ -1057,7 +1655,7 @@ package body Synth.Vhdl_Eval is
             declare
                Res : Boolean;
             begin
-               Res := Compare_Sgn_Sgn (Left, Right, Greater, +Expr) = Equal;
+               Res := Compare_Sgn_Sgn (Param1, Param2, Greater, +Expr) = Equal;
                return Create_Memory_Boolean (Res);
             end;
          when Iir_Predefined_Ieee_Numeric_Std_Eq_Sgn_Int
@@ -1066,7 +1664,7 @@ package body Synth.Vhdl_Eval is
             declare
                Res : Boolean;
             begin
-               Res := Compare_Sgn_Int (Left, Right, Greater, +Expr) = Equal;
+               Res := Compare_Sgn_Int (Param1, Param2, Greater, +Expr) = Equal;
                return Create_Memory_Boolean (Res);
             end;
          when Iir_Predefined_Ieee_Numeric_Std_Eq_Int_Sgn
@@ -1075,7 +1673,7 @@ package body Synth.Vhdl_Eval is
             declare
                Res : Boolean;
             begin
-               Res := Compare_Sgn_Int (Right, Left, Greater, +Expr) = Equal;
+               Res := Compare_Sgn_Int (Param2, Param1, Greater, +Expr) = Equal;
                return Create_Memory_Boolean (Res);
             end;
 
@@ -1083,51 +1681,51 @@ package body Synth.Vhdl_Eval is
             | Iir_Predefined_Ieee_Std_Logic_Arith_Ne_Uns_Uns
             | Iir_Predefined_Ieee_Std_Logic_Unsigned_Ne_Slv_Slv =>
             declare
-               Res : Boolean;
+               Res : Order_Type;
             begin
-               Res := Compare_Uns_Uns (Left, Right, Greater, +Expr) /= Equal;
-               return Create_Memory_Boolean (Res);
+               Res := Compare_Uns_Uns (Param1, Param2, Greater, +Expr);
+               return Create_Memory_Boolean (Res /= Equal);
             end;
          when Iir_Predefined_Ieee_Numeric_Std_Ne_Uns_Nat =>
             declare
-               Res : Boolean;
+               Res : Order_Type;
             begin
-               Res := Compare_Uns_Nat (Left, Right, Greater, +Expr) /= Equal;
-               return Create_Memory_Boolean (Res);
+               Res := Compare_Uns_Nat (Param1, Param2, Greater, +Expr);
+               return Create_Memory_Boolean (Res /= Equal);
             end;
          when Iir_Predefined_Ieee_Numeric_Std_Ne_Nat_Uns =>
             declare
-               Res : Boolean;
+               Res : Order_Type;
             begin
-               Res := Compare_Uns_Nat (Right, Left, Greater, +Expr) /= Equal;
-               return Create_Memory_Boolean (Res);
+               Res := Compare_Uns_Nat (Param2, Param1, Greater, +Expr);
+               return Create_Memory_Boolean (Res /= Equal);
             end;
          when Iir_Predefined_Ieee_Numeric_Std_Ne_Sgn_Sgn
             | Iir_Predefined_Ieee_Std_Logic_Arith_Ne_Sgn_Sgn
             | Iir_Predefined_Ieee_Std_Logic_Signed_Ne_Slv_Slv =>
             declare
-               Res : Boolean;
+               Res : Order_Type;
             begin
-               Res := Compare_Sgn_Sgn (Left, Right, Greater, +Expr) /= Equal;
-               return Create_Memory_Boolean (Res);
+               Res := Compare_Sgn_Sgn (Param1, Param2, Greater, +Expr);
+               return Create_Memory_Boolean (Res /= Equal);
             end;
          when Iir_Predefined_Ieee_Numeric_Std_Ne_Sgn_Int
             | Iir_Predefined_Ieee_Std_Logic_Arith_Ne_Sgn_Int
             | Iir_Predefined_Ieee_Std_Logic_Signed_Ne_Slv_Int =>
             declare
-               Res : Boolean;
+               Res : Order_Type;
             begin
-               Res := Compare_Sgn_Int (Left, Right, Greater, +Expr) /= Equal;
-               return Create_Memory_Boolean (Res);
+               Res := Compare_Sgn_Int (Param1, Param2, Greater, +Expr);
+               return Create_Memory_Boolean (Res /= Equal);
             end;
          when Iir_Predefined_Ieee_Numeric_Std_Ne_Int_Sgn
             | Iir_Predefined_Ieee_Std_Logic_Arith_Ne_Int_Sgn
             | Iir_Predefined_Ieee_Std_Logic_Signed_Ne_Int_Slv =>
             declare
-               Res : Boolean;
+               Res : Order_Type;
             begin
-               Res := Compare_Sgn_Int (Right, Left, Greater, +Expr) /= Equal;
-               return Create_Memory_Boolean (Res);
+               Res := Compare_Sgn_Int (Param2, Param1, Greater, +Expr);
+               return Create_Memory_Boolean (Res /= Equal);
             end;
 
          when Iir_Predefined_Ieee_Numeric_Std_Gt_Uns_Uns
@@ -1136,7 +1734,7 @@ package body Synth.Vhdl_Eval is
             declare
                Res : Boolean;
             begin
-               Res := Compare_Uns_Uns (Left, Right, Less, +Expr) = Greater;
+               Res := Compare_Uns_Uns (Param1, Param2, Less, +Expr) = Greater;
                return Create_Memory_Boolean (Res);
             end;
          when Iir_Predefined_Ieee_Numeric_Std_Gt_Sgn_Sgn
@@ -1145,21 +1743,21 @@ package body Synth.Vhdl_Eval is
             declare
                Res : Boolean;
             begin
-               Res := Compare_Sgn_Sgn (Left, Right, Less, +Expr) = Greater;
+               Res := Compare_Sgn_Sgn (Param1, Param2, Less, +Expr) = Greater;
                return Create_Memory_Boolean (Res);
             end;
          when Iir_Predefined_Ieee_Numeric_Std_Gt_Nat_Uns =>
             declare
                Res : Boolean;
             begin
-               Res := Compare_Nat_Uns (Left, Right, Less, +Expr) = Greater;
+               Res := Compare_Nat_Uns (Param1, Param2, Less, +Expr) = Greater;
                return Create_Memory_Boolean (Res);
             end;
          when Iir_Predefined_Ieee_Numeric_Std_Gt_Uns_Nat =>
             declare
                Res : Boolean;
             begin
-               Res := Compare_Uns_Nat (Left, Right, Less, +Expr) = Greater;
+               Res := Compare_Uns_Nat (Param1, Param2, Less, +Expr) = Greater;
                return Create_Memory_Boolean (Res);
             end;
          when Iir_Predefined_Ieee_Numeric_Std_Gt_Sgn_Int
@@ -1168,7 +1766,7 @@ package body Synth.Vhdl_Eval is
             declare
                Res : Boolean;
             begin
-               Res := Compare_Sgn_Int (Left, Right, Less, +Expr) = Greater;
+               Res := Compare_Sgn_Int (Param1, Param2, Less, +Expr) = Greater;
                return Create_Memory_Boolean (Res);
             end;
          when Iir_Predefined_Ieee_Numeric_Std_Gt_Int_Sgn
@@ -1177,7 +1775,7 @@ package body Synth.Vhdl_Eval is
             declare
                Res : Boolean;
             begin
-               Res := Compare_Sgn_Int (Right, Left, Greater, +Expr) < Equal;
+               Res := Compare_Sgn_Int (Param2, Param1, Greater, +Expr) < Equal;
                return Create_Memory_Boolean (Res);
             end;
 
@@ -1187,21 +1785,21 @@ package body Synth.Vhdl_Eval is
             declare
                Res : Boolean;
             begin
-               Res := Compare_Uns_Uns (Left, Right, Less, +Expr) >= Equal;
+               Res := Compare_Uns_Uns (Param1, Param2, Less, +Expr) >= Equal;
                return Create_Memory_Boolean (Res);
             end;
          when Iir_Predefined_Ieee_Numeric_Std_Ge_Nat_Uns =>
             declare
                Res : Boolean;
             begin
-               Res := Compare_Nat_Uns (Left, Right, Less, +Expr) >= Equal;
+               Res := Compare_Nat_Uns (Param1, Param2, Less, +Expr) >= Equal;
                return Create_Memory_Boolean (Res);
             end;
          when Iir_Predefined_Ieee_Numeric_Std_Ge_Uns_Nat =>
             declare
                Res : Boolean;
             begin
-               Res := Compare_Uns_Nat (Left, Right, Less, +Expr) >= Equal;
+               Res := Compare_Uns_Nat (Param1, Param2, Less, +Expr) >= Equal;
                return Create_Memory_Boolean (Res);
             end;
          when Iir_Predefined_Ieee_Numeric_Std_Ge_Sgn_Sgn
@@ -1210,7 +1808,7 @@ package body Synth.Vhdl_Eval is
             declare
                Res : Boolean;
             begin
-               Res := Compare_Sgn_Sgn (Left, Right, Less, +Expr) >= Equal;
+               Res := Compare_Sgn_Sgn (Param1, Param2, Less, +Expr) >= Equal;
                return Create_Memory_Boolean (Res);
             end;
          when Iir_Predefined_Ieee_Numeric_Std_Ge_Sgn_Int
@@ -1219,50 +1817,50 @@ package body Synth.Vhdl_Eval is
             declare
                Res : Boolean;
             begin
-               Res := Compare_Sgn_Int (Left, Right, Less, +Expr) >= Equal;
+               Res := Compare_Sgn_Int (Param1, Param2, Less, +Expr) >= Equal;
                return Create_Memory_Boolean (Res);
             end;
          when Iir_Predefined_Ieee_Numeric_Std_Ge_Int_Sgn
             | Iir_Predefined_Ieee_Std_Logic_Arith_Ge_Int_Sgn
             | Iir_Predefined_Ieee_Std_Logic_Signed_Ge_Int_Slv =>
             declare
-               Res : Boolean;
+               Res : Order_Type;
             begin
-               Res := Compare_Sgn_Int (Right, Left, Greater, +Expr) <= Equal;
-               return Create_Memory_Boolean (Res);
+               Res := Compare_Sgn_Int (Param2, Param1, Greater, +Expr);
+               return Create_Memory_Boolean (Res <= Equal);
             end;
 
          when Iir_Predefined_Ieee_Numeric_Std_Le_Uns_Uns
             | Iir_Predefined_Ieee_Std_Logic_Arith_Le_Uns_Uns
             | Iir_Predefined_Ieee_Std_Logic_Unsigned_Le_Slv_Slv =>
             declare
-               Res : Boolean;
+               Res : Order_Type;
             begin
-               Res := Compare_Uns_Uns (Left, Right, Greater, +Expr) <= Equal;
-               return Create_Memory_Boolean (Res);
+               Res := Compare_Uns_Uns (Param1, Param2, Greater, +Expr);
+               return Create_Memory_Boolean (Res <= Equal);
             end;
          when Iir_Predefined_Ieee_Numeric_Std_Le_Uns_Nat =>
             declare
-               Res : Boolean;
+               Res : Order_Type;
             begin
-               Res := Compare_Uns_Nat (Left, Right, Greater, +Expr) <= Equal;
-               return Create_Memory_Boolean (Res);
+               Res := Compare_Uns_Nat (Param1, Param2, Greater, +Expr);
+               return Create_Memory_Boolean (Res <= Equal);
             end;
          when Iir_Predefined_Ieee_Numeric_Std_Le_Nat_Uns =>
             declare
-               Res : Boolean;
+               Res : Order_Type;
             begin
-               Res := Compare_Nat_Uns (Left, Right, Greater, +Expr) <= Equal;
-               return Create_Memory_Boolean (Res);
+               Res := Compare_Nat_Uns (Param1, Param2, Greater, +Expr);
+               return Create_Memory_Boolean (Res <= Equal);
             end;
          when Iir_Predefined_Ieee_Numeric_Std_Le_Sgn_Sgn
             | Iir_Predefined_Ieee_Std_Logic_Arith_Le_Sgn_Sgn
             | Iir_Predefined_Ieee_Std_Logic_Signed_Le_Slv_Slv =>
             declare
-               Res : Boolean;
+               Res : Order_Type;
             begin
-               Res := Compare_Sgn_Sgn (Left, Right, Greater, +Expr) <= Equal;
-               return Create_Memory_Boolean (Res);
+               Res := Compare_Sgn_Sgn (Param1, Param2, Greater, +Expr);
+               return Create_Memory_Boolean (Res <= Equal);
             end;
          when Iir_Predefined_Ieee_Numeric_Std_Le_Int_Sgn
             | Iir_Predefined_Ieee_Std_Logic_Arith_Le_Int_Sgn
@@ -1270,17 +1868,17 @@ package body Synth.Vhdl_Eval is
             declare
                Res : Boolean;
             begin
-               Res := Compare_Sgn_Int (Right, Left, Less, +Expr) >= Equal;
+               Res := Compare_Sgn_Int (Param2, Param1, Less, +Expr) >= Equal;
                return Create_Memory_Boolean (Res);
             end;
          when Iir_Predefined_Ieee_Numeric_Std_Le_Sgn_Int
             | Iir_Predefined_Ieee_Std_Logic_Arith_Le_Sgn_Int
             | Iir_Predefined_Ieee_Std_Logic_Signed_Le_Slv_Int =>
             declare
-               Res : Boolean;
+               Res : Order_Type;
             begin
-               Res := Compare_Sgn_Int (Left, Right, Greater, +Expr) <= Equal;
-               return Create_Memory_Boolean (Res);
+               Res := Compare_Sgn_Int (Param1, Param2, Greater, +Expr);
+               return Create_Memory_Boolean (Res <= Equal);
             end;
 
          when Iir_Predefined_Ieee_Numeric_Std_Lt_Uns_Uns
@@ -1289,21 +1887,21 @@ package body Synth.Vhdl_Eval is
             declare
                Res : Boolean;
             begin
-               Res := Compare_Uns_Uns (Left, Right, Greater, +Expr) < Equal;
+               Res := Compare_Uns_Uns (Param1, Param2, Greater, +Expr) < Equal;
                return Create_Memory_Boolean (Res);
             end;
          when Iir_Predefined_Ieee_Numeric_Std_Lt_Uns_Nat =>
             declare
                Res : Boolean;
             begin
-               Res := Compare_Uns_Nat (Left, Right, Greater, +Expr) < Equal;
+               Res := Compare_Uns_Nat (Param1, Param2, Greater, +Expr) < Equal;
                return Create_Memory_Boolean (Res);
             end;
          when Iir_Predefined_Ieee_Numeric_Std_Lt_Nat_Uns =>
             declare
                Res : Boolean;
             begin
-               Res := Compare_Nat_Uns (Left, Right, Greater, +Expr) < Equal;
+               Res := Compare_Nat_Uns (Param1, Param2, Greater, +Expr) < Equal;
                return Create_Memory_Boolean (Res);
             end;
          when Iir_Predefined_Ieee_Numeric_Std_Lt_Sgn_Sgn
@@ -1312,7 +1910,7 @@ package body Synth.Vhdl_Eval is
             declare
                Res : Boolean;
             begin
-               Res := Compare_Sgn_Sgn (Left, Right, Greater, +Expr) < Equal;
+               Res := Compare_Sgn_Sgn (Param1, Param2, Greater, +Expr) < Equal;
                return Create_Memory_Boolean (Res);
             end;
          when Iir_Predefined_Ieee_Numeric_Std_Lt_Int_Sgn
@@ -1321,7 +1919,7 @@ package body Synth.Vhdl_Eval is
             declare
                Res : Boolean;
             begin
-               Res := Compare_Sgn_Int (Right, Left, Less, +Expr) > Equal;
+               Res := Compare_Sgn_Int (Param2, Param1, Less, +Expr) > Equal;
                return Create_Memory_Boolean (Res);
             end;
          when Iir_Predefined_Ieee_Numeric_Std_Lt_Sgn_Int
@@ -1330,7 +1928,7 @@ package body Synth.Vhdl_Eval is
             declare
                Res : Boolean;
             begin
-               Res := Compare_Sgn_Int (Left, Right, Greater, +Expr) < Equal;
+               Res := Compare_Sgn_Int (Param1, Param2, Greater, +Expr) < Equal;
                return Create_Memory_Boolean (Res);
             end;
 
@@ -1338,14 +1936,14 @@ package body Synth.Vhdl_Eval is
             declare
                Res : Order_Type;
             begin
-               Res := Compare_Uns_Sgn (Left, Right, +Expr);
+               Res := Compare_Uns_Sgn (Param1, Param2, +Expr);
                return Create_Memory_Boolean (Res < Equal);
             end;
          when Iir_Predefined_Ieee_Std_Logic_Arith_Lt_Sgn_Uns =>
             declare
                Res : Order_Type;
             begin
-               Res := Compare_Uns_Sgn (Right, Left, +Expr);
+               Res := Compare_Uns_Sgn (Param2, Param1, +Expr);
                return Create_Memory_Boolean (Res > Equal);
             end;
          when Iir_Predefined_Ieee_Std_Logic_Arith_Lt_Uns_Int
@@ -1353,7 +1951,7 @@ package body Synth.Vhdl_Eval is
             declare
                Res : Order_Type;
             begin
-               Res := Compare_Uns_Int (Left, Read_Discrete (Right), +Expr);
+               Res := Compare_Uns_Int (Param1, Read_Discrete (Param2), +Expr);
                return Create_Memory_Boolean (Res < Equal);
             end;
          when Iir_Predefined_Ieee_Std_Logic_Arith_Lt_Int_Uns
@@ -1361,7 +1959,7 @@ package body Synth.Vhdl_Eval is
             declare
                Res : Order_Type;
             begin
-               Res := Compare_Uns_Int (Right, Read_Discrete (Left), +Expr);
+               Res := Compare_Uns_Int (Param2, Read_Discrete (Param1), +Expr);
                return Create_Memory_Boolean (Res > Equal);
             end;
 
@@ -1369,14 +1967,14 @@ package body Synth.Vhdl_Eval is
             declare
                Res : Order_Type;
             begin
-               Res := Compare_Uns_Sgn (Left, Right, +Expr);
+               Res := Compare_Uns_Sgn (Param1, Param2, +Expr);
                return Create_Memory_Boolean (Res <= Equal);
             end;
          when Iir_Predefined_Ieee_Std_Logic_Arith_Le_Sgn_Uns =>
             declare
                Res : Order_Type;
             begin
-               Res := Compare_Uns_Sgn (Right, Left, +Expr);
+               Res := Compare_Uns_Sgn (Param2, Param1, +Expr);
                return Create_Memory_Boolean (Res >= Equal);
             end;
          when Iir_Predefined_Ieee_Std_Logic_Arith_Le_Uns_Int
@@ -1384,7 +1982,7 @@ package body Synth.Vhdl_Eval is
             declare
                Res : Order_Type;
             begin
-               Res := Compare_Uns_Int (Left, Read_Discrete (Right), +Expr);
+               Res := Compare_Uns_Int (Param1, Read_Discrete (Param2), +Expr);
                return Create_Memory_Boolean (Res <= Equal);
             end;
          when Iir_Predefined_Ieee_Std_Logic_Arith_Le_Int_Uns
@@ -1392,7 +1990,7 @@ package body Synth.Vhdl_Eval is
             declare
                Res : Order_Type;
             begin
-               Res := Compare_Uns_Int (Right, Read_Discrete (Left), +Expr);
+               Res := Compare_Uns_Int (Param2, Read_Discrete (Param1), +Expr);
                return Create_Memory_Boolean (Res >= Equal);
             end;
 
@@ -1400,14 +1998,14 @@ package body Synth.Vhdl_Eval is
             declare
                Res : Order_Type;
             begin
-               Res := Compare_Uns_Sgn (Left, Right, +Expr);
+               Res := Compare_Uns_Sgn (Param1, Param2, +Expr);
                return Create_Memory_Boolean (Res > Equal);
             end;
          when Iir_Predefined_Ieee_Std_Logic_Arith_Gt_Sgn_Uns =>
             declare
                Res : Order_Type;
             begin
-               Res := Compare_Uns_Sgn (Right, Left, +Expr);
+               Res := Compare_Uns_Sgn (Param2, Param1, +Expr);
                return Create_Memory_Boolean (Res < Equal);
             end;
          when Iir_Predefined_Ieee_Std_Logic_Arith_Gt_Uns_Int
@@ -1415,7 +2013,7 @@ package body Synth.Vhdl_Eval is
             declare
                Res : Order_Type;
             begin
-               Res := Compare_Uns_Int (Left, Read_Discrete (Right), +Expr);
+               Res := Compare_Uns_Int (Param1, Read_Discrete (Param2), +Expr);
                return Create_Memory_Boolean (Res > Equal);
             end;
          when Iir_Predefined_Ieee_Std_Logic_Arith_Gt_Int_Uns
@@ -1423,7 +2021,7 @@ package body Synth.Vhdl_Eval is
             declare
                Res : Order_Type;
             begin
-               Res := Compare_Uns_Int (Right, Read_Discrete (Left), +Expr);
+               Res := Compare_Uns_Int (Param2, Read_Discrete (Param1), +Expr);
                return Create_Memory_Boolean (Res < Equal);
             end;
 
@@ -1431,14 +2029,14 @@ package body Synth.Vhdl_Eval is
             declare
                Res : Order_Type;
             begin
-               Res := Compare_Uns_Sgn (Left, Right, +Expr);
+               Res := Compare_Uns_Sgn (Param1, Param2, +Expr);
                return Create_Memory_Boolean (Res >= Equal);
             end;
          when Iir_Predefined_Ieee_Std_Logic_Arith_Ge_Sgn_Uns =>
             declare
                Res : Order_Type;
             begin
-               Res := Compare_Uns_Sgn (Right, Left, +Expr);
+               Res := Compare_Uns_Sgn (Param2, Param1, +Expr);
                return Create_Memory_Boolean (Res <= Equal);
             end;
          when Iir_Predefined_Ieee_Std_Logic_Arith_Ge_Uns_Int
@@ -1446,7 +2044,7 @@ package body Synth.Vhdl_Eval is
             declare
                Res : Order_Type;
             begin
-               Res := Compare_Uns_Int (Left, Read_Discrete (Right), +Expr);
+               Res := Compare_Uns_Int (Param1, Read_Discrete (Param2), +Expr);
                return Create_Memory_Boolean (Res >= Equal);
             end;
          when Iir_Predefined_Ieee_Std_Logic_Arith_Ge_Int_Uns
@@ -1454,7 +2052,7 @@ package body Synth.Vhdl_Eval is
             declare
                Res : Order_Type;
             begin
-               Res := Compare_Uns_Int (Right, Read_Discrete (Left), +Expr);
+               Res := Compare_Uns_Int (Param2, Read_Discrete (Param1), +Expr);
                return Create_Memory_Boolean (Res <= Equal);
             end;
 
@@ -1462,14 +2060,14 @@ package body Synth.Vhdl_Eval is
             declare
                Res : Order_Type;
             begin
-               Res := Compare_Uns_Sgn (Left, Right, +Expr);
+               Res := Compare_Uns_Sgn (Param1, Param2, +Expr);
                return Create_Memory_Boolean (Res = Equal);
             end;
          when Iir_Predefined_Ieee_Std_Logic_Arith_Eq_Sgn_Uns =>
             declare
                Res : Order_Type;
             begin
-               Res := Compare_Uns_Sgn (Right, Left, +Expr);
+               Res := Compare_Uns_Sgn (Param2, Param1, +Expr);
                return Create_Memory_Boolean (Res = Equal);
             end;
          when Iir_Predefined_Ieee_Std_Logic_Arith_Eq_Uns_Int
@@ -1477,7 +2075,7 @@ package body Synth.Vhdl_Eval is
             declare
                Res : Order_Type;
             begin
-               Res := Compare_Uns_Int (Left, Read_Discrete (Right), +Expr);
+               Res := Compare_Uns_Int (Param1, Read_Discrete (Param2), +Expr);
                return Create_Memory_Boolean (Res = Equal);
             end;
          when Iir_Predefined_Ieee_Std_Logic_Arith_Eq_Int_Uns
@@ -1485,7 +2083,7 @@ package body Synth.Vhdl_Eval is
             declare
                Res : Order_Type;
             begin
-               Res := Compare_Uns_Int (Right, Read_Discrete (Left), +Expr);
+               Res := Compare_Uns_Int (Param2, Read_Discrete (Param1), +Expr);
                return Create_Memory_Boolean (Res = Equal);
             end;
 
@@ -1493,14 +2091,14 @@ package body Synth.Vhdl_Eval is
             declare
                Res : Order_Type;
             begin
-               Res := Compare_Uns_Sgn (Left, Right, +Expr);
+               Res := Compare_Uns_Sgn (Param1, Param2, +Expr);
                return Create_Memory_Boolean (Res /= Equal);
             end;
          when Iir_Predefined_Ieee_Std_Logic_Arith_Ne_Sgn_Uns =>
             declare
                Res : Order_Type;
             begin
-               Res := Compare_Uns_Sgn (Right, Left, +Expr);
+               Res := Compare_Uns_Sgn (Param2, Param1, +Expr);
                return Create_Memory_Boolean (Res /= Equal);
             end;
          when Iir_Predefined_Ieee_Std_Logic_Arith_Ne_Uns_Int
@@ -1508,7 +2106,7 @@ package body Synth.Vhdl_Eval is
             declare
                Res : Order_Type;
             begin
-               Res := Compare_Uns_Int (Left, Read_Discrete (Right), +Expr);
+               Res := Compare_Uns_Int (Param1, Read_Discrete (Param2), +Expr);
                return Create_Memory_Boolean (Res /= Equal);
             end;
          when Iir_Predefined_Ieee_Std_Logic_Arith_Ne_Int_Uns
@@ -1516,7 +2114,7 @@ package body Synth.Vhdl_Eval is
             declare
                Res : Order_Type;
             begin
-               Res := Compare_Uns_Int (Right, Read_Discrete (Left), +Expr);
+               Res := Compare_Uns_Int (Param2, Read_Discrete (Param1), +Expr);
                return Create_Memory_Boolean (Res /= Equal);
             end;
 
@@ -1525,231 +2123,237 @@ package body Synth.Vhdl_Eval is
             | Iir_Predefined_Ieee_Std_Logic_Arith_Add_Uns_Uns_Slv
             | Iir_Predefined_Ieee_Std_Logic_Arith_Add_Uns_Uns_Uns
             | Iir_Predefined_Ieee_Numeric_Std_Unsigned_Add_Slv_Slv =>
-            return Add_Uns_Uns (Left, Right, +Expr);
+            return Add_Uns_Uns (Param1, Param2, +Expr);
 
          when Iir_Predefined_Ieee_Numeric_Std_Add_Uns_Log
            | Iir_Predefined_Ieee_Std_Logic_Unsigned_Add_Slv_Log =>
-            return Add_Uns_Uns (Left, Log_To_Vec (Right, Left), +Expr);
+            return Add_Uns_Uns (Param1, Log_To_Vec (Param2, Param1), +Expr);
 
          when Iir_Predefined_Ieee_Numeric_Std_Add_Log_Uns
             | Iir_Predefined_Ieee_Std_Logic_Unsigned_Add_Log_Slv =>
-            return Add_Uns_Uns (Log_To_Vec (Left, Right), Right, +Expr);
+            return Add_Uns_Uns (Log_To_Vec (Param1, Param2), Param2, +Expr);
 
          when Iir_Predefined_Ieee_Numeric_Std_Add_Uns_Nat
             | Iir_Predefined_Ieee_Std_Logic_Unsigned_Add_Slv_Int
             | Iir_Predefined_Ieee_Numeric_Std_Unsigned_Add_Slv_Nat =>
-            return Add_Uns_Nat (Left, To_Uns64 (Read_Discrete (Right)), +Expr);
+            return Add_Uns_Nat
+              (Param1, To_Uns64 (Read_Discrete (Param2)), +Expr);
          when Iir_Predefined_Ieee_Numeric_Std_Add_Nat_Uns
             | Iir_Predefined_Ieee_Numeric_Std_Unsigned_Add_Nat_Slv
             | Iir_Predefined_Ieee_Std_Logic_Unsigned_Add_Int_Slv =>
-            return Add_Uns_Nat (Right, To_Uns64 (Read_Discrete (Left)), +Expr);
+            return Add_Uns_Nat
+              (Param2, To_Uns64 (Read_Discrete (Param1)), +Expr);
 
          when Iir_Predefined_Ieee_Numeric_Std_Add_Sgn_Sgn
             | Iir_Predefined_Ieee_Std_Logic_Arith_Add_Sgn_Sgn_Sgn
             | Iir_Predefined_Ieee_Std_Logic_Arith_Add_Sgn_Sgn_Slv
             | Iir_Predefined_Ieee_Std_Logic_Signed_Add_Slv_Slv =>
-            return Add_Sgn_Sgn (Left, Right, +Expr);
+            return Add_Sgn_Sgn (Param1, Param2, +Expr);
          when Iir_Predefined_Ieee_Numeric_Std_Add_Sgn_Int
             | Iir_Predefined_Ieee_Std_Logic_Signed_Add_Slv_Int =>
-            return Add_Sgn_Int (Left, Read_Discrete (Right), +Expr);
+            return Add_Sgn_Int (Param1, Read_Discrete (Param2), +Expr);
          when Iir_Predefined_Ieee_Numeric_Std_Add_Int_Sgn
             | Iir_Predefined_Ieee_Std_Logic_Signed_Add_Int_Slv =>
-            return Add_Sgn_Int (Right, Read_Discrete (Left), +Expr);
+            return Add_Sgn_Int (Param2, Read_Discrete (Param1), +Expr);
 
          when Iir_Predefined_Ieee_Numeric_Std_Add_Sgn_Log
             | Iir_Predefined_Ieee_Std_Logic_Signed_Add_Slv_Log =>
-            return Add_Sgn_Sgn (Left, Log_To_Vec (Right, Left), +Expr);
+            return Add_Sgn_Sgn (Param1, Log_To_Vec (Param2, Param1), +Expr);
          when Iir_Predefined_Ieee_Numeric_Std_Add_Log_Sgn
             | Iir_Predefined_Ieee_Std_Logic_Signed_Add_Log_Slv =>
-            return Add_Sgn_Sgn (Log_To_Vec (Left, Right), Right, +Expr);
+            return Add_Sgn_Sgn (Log_To_Vec (Param1, Param2), Param2, +Expr);
 
          --  std_logic_arith."+"
          when Iir_Predefined_Ieee_Std_Logic_Arith_Add_Uns_Sgn_Sgn
             | Iir_Predefined_Ieee_Std_Logic_Arith_Add_Uns_Sgn_Slv =>
-            return Add_Uns_Sgn_Sgn (Left, Right, +Expr);
+            return Add_Uns_Sgn_Sgn (Param1, Param2, +Expr);
          when Iir_Predefined_Ieee_Std_Logic_Arith_Add_Sgn_Uns_Sgn
             | Iir_Predefined_Ieee_Std_Logic_Arith_Add_Sgn_Uns_Slv =>
-            return Add_Sgn_Uns_Sgn (Left, Right, +Expr);
+            return Add_Sgn_Uns_Sgn (Param1, Param2, +Expr);
          when Iir_Predefined_Ieee_Std_Logic_Arith_Add_Uns_Int_Uns
             | Iir_Predefined_Ieee_Std_Logic_Arith_Add_Uns_Int_Slv =>
-            return Add_Uns_Int_Uns (Left, Read_Discrete (Right), +Expr);
+            return Add_Uns_Int_Uns (Param1, Read_Discrete (Param2), +Expr);
          when Iir_Predefined_Ieee_Std_Logic_Arith_Add_Int_Uns_Uns
             | Iir_Predefined_Ieee_Std_Logic_Arith_Add_Int_Uns_Slv =>
-            return Add_Uns_Int_Uns (Right, Read_Discrete (Left), +Expr);
+            return Add_Uns_Int_Uns (Param2, Read_Discrete (Param1), +Expr);
          when Iir_Predefined_Ieee_Std_Logic_Arith_Add_Sgn_Int_Sgn
             | Iir_Predefined_Ieee_Std_Logic_Arith_Add_Sgn_Int_Slv =>
-            return Add_Sgn_Int_Sgn (Left, Read_Discrete (Right), +Expr);
+            return Add_Sgn_Int_Sgn (Param1, Read_Discrete (Param2), +Expr);
          when Iir_Predefined_Ieee_Std_Logic_Arith_Add_Int_Sgn_Sgn
             | Iir_Predefined_Ieee_Std_Logic_Arith_Add_Int_Sgn_Slv =>
-            return Add_Sgn_Int_Sgn (Right, Read_Discrete (Left), +Expr);
+            return Add_Sgn_Int_Sgn (Param2, Read_Discrete (Param1), +Expr);
          when Iir_Predefined_Ieee_Std_Logic_Arith_Add_Uns_Log_Uns
             | Iir_Predefined_Ieee_Std_Logic_Arith_Add_Uns_Log_Slv =>
-            return Add_Uns_Log_Uns (Left, Right, +Expr);
+            return Add_Uns_Log_Uns (Param1, Param2, +Expr);
          when Iir_Predefined_Ieee_Std_Logic_Arith_Add_Log_Uns_Uns
             | Iir_Predefined_Ieee_Std_Logic_Arith_Add_Log_Uns_Slv =>
-            return Add_Uns_Log_Uns (Right, Left, +Expr);
+            return Add_Uns_Log_Uns (Param2, Param1, +Expr);
          when Iir_Predefined_Ieee_Std_Logic_Arith_Add_Sgn_Log_Sgn
             | Iir_Predefined_Ieee_Std_Logic_Arith_Add_Sgn_Log_Slv =>
-            return Add_Sgn_Log_Sgn (Left, Right, +Expr);
+            return Add_Sgn_Log_Sgn (Param1, Param2, +Expr);
          when Iir_Predefined_Ieee_Std_Logic_Arith_Add_Log_Sgn_Sgn
             | Iir_Predefined_Ieee_Std_Logic_Arith_Add_Log_Sgn_Slv =>
-            return Add_Sgn_Log_Sgn (Right, Left, +Expr);
+            return Add_Sgn_Log_Sgn (Param2, Param1, +Expr);
 
          when Iir_Predefined_Ieee_Numeric_Std_Sub_Uns_Uns
             | Iir_Predefined_Ieee_Numeric_Std_Unsigned_Sub_Slv_Slv
             | Iir_Predefined_Ieee_Std_Logic_Arith_Sub_Uns_Uns_Slv
             | Iir_Predefined_Ieee_Std_Logic_Arith_Sub_Uns_Uns_Uns
             | Iir_Predefined_Ieee_Std_Logic_Unsigned_Sub_Slv_Slv =>
-            return Sub_Uns_Uns (Left, Right, +Expr);
+            return Sub_Uns_Uns (Param1, Param2, +Expr);
          when Iir_Predefined_Ieee_Numeric_Std_Sub_Uns_Nat
             | Iir_Predefined_Ieee_Numeric_Std_Unsigned_Sub_Slv_Nat
             | Iir_Predefined_Ieee_Std_Logic_Unsigned_Sub_Slv_Int =>
-            return Sub_Uns_Nat (Left, To_Uns64 (Read_Discrete (Right)), +Expr);
+            return Sub_Uns_Nat
+              (Param1, To_Uns64 (Read_Discrete (Param2)), +Expr);
          when Iir_Predefined_Ieee_Numeric_Std_Sub_Nat_Uns
             | Iir_Predefined_Ieee_Numeric_Std_Unsigned_Sub_Nat_Slv
             | Iir_Predefined_Ieee_Std_Logic_Unsigned_Sub_Int_Slv =>
-            return Sub_Nat_Uns (To_Uns64 (Read_Discrete (Left)), Right, +Expr);
+            return Sub_Nat_Uns
+              (To_Uns64 (Read_Discrete (Param1)), Param2, +Expr);
 
          when Iir_Predefined_Ieee_Numeric_Std_Sub_Uns_Log
             | Iir_Predefined_Ieee_Std_Logic_Unsigned_Sub_Slv_Log =>
-            return Sub_Uns_Uns (Left, Log_To_Vec (Right, Left), +Expr);
+            return Sub_Uns_Uns (Param1, Log_To_Vec (Param2, Param1), +Expr);
          when Iir_Predefined_Ieee_Numeric_Std_Sub_Log_Uns
             | Iir_Predefined_Ieee_Std_Logic_Unsigned_Sub_Log_Slv =>
-            return Sub_Uns_Uns (Log_To_Vec (Left, Right), Right, +Expr);
+            return Sub_Uns_Uns (Log_To_Vec (Param1, Param2), Param2, +Expr);
 
          when Iir_Predefined_Ieee_Numeric_Std_Sub_Sgn_Sgn
             | Iir_Predefined_Ieee_Std_Logic_Arith_Sub_Sgn_Sgn_Slv
             | Iir_Predefined_Ieee_Std_Logic_Arith_Sub_Sgn_Sgn_Sgn
             | Iir_Predefined_Ieee_Std_Logic_Signed_Sub_Slv_Slv =>
-            return Sub_Sgn_Sgn (Left, Right, +Expr);
+            return Sub_Sgn_Sgn (Param1, Param2, +Expr);
          when Iir_Predefined_Ieee_Numeric_Std_Sub_Sgn_Int
             | Iir_Predefined_Ieee_Std_Logic_Signed_Sub_Slv_Int =>
-            return Sub_Sgn_Int (Left, Read_Discrete (Right), +Expr);
+            return Sub_Sgn_Int (Param1, Read_Discrete (Param2), +Expr);
          when Iir_Predefined_Ieee_Numeric_Std_Sub_Int_Sgn
             | Iir_Predefined_Ieee_Std_Logic_Signed_Sub_Int_Slv =>
-            return Sub_Int_Sgn (Read_Discrete (Left), Right, +Expr);
+            return Sub_Int_Sgn (Read_Discrete (Param1), Param2, +Expr);
 
          when Iir_Predefined_Ieee_Numeric_Std_Sub_Sgn_Log
             | Iir_Predefined_Ieee_Std_Logic_Signed_Sub_Slv_Log =>
-            return Sub_Sgn_Sgn (Left, Log_To_Vec (Right, Left), +Expr);
+            return Sub_Sgn_Sgn (Param1, Log_To_Vec (Param2, Param1), +Expr);
          when Iir_Predefined_Ieee_Numeric_Std_Sub_Log_Sgn
             | Iir_Predefined_Ieee_Std_Logic_Signed_Sub_Log_Slv =>
-            return Sub_Sgn_Sgn (Log_To_Vec (Left, Right), Right, +Expr);
+            return Sub_Sgn_Sgn (Log_To_Vec (Param1, Param2), Param2, +Expr);
 
          --  std_logic_arith."-"
          when Iir_Predefined_Ieee_Std_Logic_Arith_Sub_Uns_Sgn_Sgn
             | Iir_Predefined_Ieee_Std_Logic_Arith_Sub_Uns_Sgn_Slv =>
-            return Sub_Uns_Sgn_Sgn (Left, Right, +Expr);
+            return Sub_Uns_Sgn_Sgn (Param1, Param2, +Expr);
          when Iir_Predefined_Ieee_Std_Logic_Arith_Sub_Sgn_Uns_Sgn
             | Iir_Predefined_Ieee_Std_Logic_Arith_Sub_Sgn_Uns_Slv =>
-            return Sub_Sgn_Uns_Sgn (Left, Right, +Expr);
+            return Sub_Sgn_Uns_Sgn (Param1, Param2, +Expr);
          when Iir_Predefined_Ieee_Std_Logic_Arith_Sub_Uns_Int_Uns
             | Iir_Predefined_Ieee_Std_Logic_Arith_Sub_Uns_Int_Slv =>
-            return Sub_Uns_Int_Uns (Left, Read_Discrete (Right), +Expr);
+            return Sub_Uns_Int_Uns (Param1, Read_Discrete (Param2), +Expr);
          when Iir_Predefined_Ieee_Std_Logic_Arith_Sub_Int_Uns_Uns
             | Iir_Predefined_Ieee_Std_Logic_Arith_Sub_Int_Uns_Slv =>
-            return Sub_Int_Uns_Uns (Read_Discrete (Left), Right, +Expr);
+            return Sub_Int_Uns_Uns (Read_Discrete (Param1), Param2, +Expr);
          when Iir_Predefined_Ieee_Std_Logic_Arith_Sub_Sgn_Int_Sgn
             | Iir_Predefined_Ieee_Std_Logic_Arith_Sub_Sgn_Int_Slv =>
-            return Sub_Sgn_Int_Sgn (Left, Read_Discrete (Right), +Expr);
+            return Sub_Sgn_Int_Sgn (Param1, Read_Discrete (Param2), +Expr);
          when Iir_Predefined_Ieee_Std_Logic_Arith_Sub_Int_Sgn_Sgn
             | Iir_Predefined_Ieee_Std_Logic_Arith_Sub_Int_Sgn_Slv =>
-            return Sub_Int_Sgn_Sgn (Read_Discrete (Left), Right, +Expr);
+            return Sub_Int_Sgn_Sgn (Read_Discrete (Param1), Param2, +Expr);
          when Iir_Predefined_Ieee_Std_Logic_Arith_Sub_Uns_Log_Uns
             | Iir_Predefined_Ieee_Std_Logic_Arith_Sub_Uns_Log_Slv =>
-            return Sub_Uns_Log_Uns (Left, Right, +Expr);
+            return Sub_Uns_Log_Uns (Param1, Param2, +Expr);
          when Iir_Predefined_Ieee_Std_Logic_Arith_Sub_Log_Uns_Uns
             | Iir_Predefined_Ieee_Std_Logic_Arith_Sub_Log_Uns_Slv =>
-            return Sub_Log_Uns_Uns (Left, Right, +Expr);
+            return Sub_Log_Uns_Uns (Param1, Param2, +Expr);
          when Iir_Predefined_Ieee_Std_Logic_Arith_Sub_Sgn_Log_Sgn
             | Iir_Predefined_Ieee_Std_Logic_Arith_Sub_Sgn_Log_Slv =>
-            return Sub_Sgn_Log_Sgn (Left, Right, +Expr);
+            return Sub_Sgn_Log_Sgn (Param1, Param2, +Expr);
          when Iir_Predefined_Ieee_Std_Logic_Arith_Sub_Log_Sgn_Sgn
             | Iir_Predefined_Ieee_Std_Logic_Arith_Sub_Log_Sgn_Slv =>
-            return Sub_Log_Sgn_Sgn (Left, Right, +Expr);
+            return Sub_Log_Sgn_Sgn (Param1, Param2, +Expr);
 
          when Iir_Predefined_Ieee_Numeric_Std_Mul_Uns_Uns =>
-            return Mul_Uns_Uns (Left, Right, +Expr);
+            return Mul_Uns_Uns (Param1, Param2, +Expr);
          when Iir_Predefined_Ieee_Numeric_Std_Mul_Nat_Uns =>
-            return Mul_Nat_Uns (To_Uns64 (Read_Discrete (Left)), Right, +Expr);
+            return Mul_Nat_Uns
+              (To_Uns64 (Read_Discrete (Param1)), Param2, +Expr);
          when Iir_Predefined_Ieee_Numeric_Std_Mul_Uns_Nat =>
-            return Mul_Uns_Nat (Left, To_Uns64 (Read_Discrete (Right)), +Expr);
+            return Mul_Uns_Nat
+              (Param1, To_Uns64 (Read_Discrete (Param2)), +Expr);
 
          when Iir_Predefined_Ieee_Numeric_Std_Mul_Sgn_Sgn =>
-            return Mul_Sgn_Sgn (Left, Right, +Expr);
+            return Mul_Sgn_Sgn (Param1, Param2, +Expr);
          when Iir_Predefined_Ieee_Numeric_Std_Mul_Sgn_Int =>
-            return Mul_Sgn_Int (Left, Read_Discrete (Right), +Expr);
+            return Mul_Sgn_Int (Param1, Read_Discrete (Param2), +Expr);
          when Iir_Predefined_Ieee_Numeric_Std_Mul_Int_Sgn =>
-            return Mul_Int_Sgn (Read_Discrete (Left), Right, +Expr);
+            return Mul_Int_Sgn (Read_Discrete (Param1), Param2, +Expr);
 
          --  std_logic_arith."*"
          when Iir_Predefined_Ieee_Std_Logic_Arith_Mul_Uns_Uns_Uns
             | Iir_Predefined_Ieee_Std_Logic_Arith_Mul_Uns_Uns_Slv
             | Iir_Predefined_Ieee_Std_Logic_Unsigned_Mul_Slv_Slv =>
-            return Mul_Uns_Uns_Uns (Left, Right, +Expr);
+            return Mul_Uns_Uns_Uns (Param1, Param2, +Expr);
          when Iir_Predefined_Ieee_Std_Logic_Arith_Mul_Sgn_Sgn_Sgn
             | Iir_Predefined_Ieee_Std_Logic_Arith_Mul_Sgn_Sgn_Slv
             | Iir_Predefined_Ieee_Std_Logic_Signed_Mul_Slv_Slv =>
-            return Mul_Sgn_Sgn_Sgn (Left, Right, +Expr);
+            return Mul_Sgn_Sgn_Sgn (Param1, Param2, +Expr);
          when Iir_Predefined_Ieee_Std_Logic_Arith_Mul_Uns_Sgn_Sgn
             | Iir_Predefined_Ieee_Std_Logic_Arith_Mul_Uns_Sgn_Slv =>
-            return Mul_Uns_Sgn_Sgn (Left, Right, +Expr);
+            return Mul_Uns_Sgn_Sgn (Param1, Param2, +Expr);
          when Iir_Predefined_Ieee_Std_Logic_Arith_Mul_Sgn_Uns_Sgn
             | Iir_Predefined_Ieee_Std_Logic_Arith_Mul_Sgn_Uns_Slv =>
-            return Mul_Sgn_Uns_Sgn (Left, Right, +Expr);
+            return Mul_Sgn_Uns_Sgn (Param1, Param2, +Expr);
 
          when Iir_Predefined_Ieee_Numeric_Std_Div_Uns_Uns =>
-            return Div_Uns_Uns (Inst, Left, Right, Expr);
+            return Div_Uns_Uns (Inst, Param1, Param2, Expr);
          when Iir_Predefined_Ieee_Numeric_Std_Div_Uns_Nat =>
             return Div_Uns_Nat
-              (Inst, Left, To_Uns64 (Read_Discrete (Right)), Expr);
+              (Inst, Param1, To_Uns64 (Read_Discrete (Param2)), Expr);
          when Iir_Predefined_Ieee_Numeric_Std_Div_Nat_Uns =>
             return Div_Nat_Uns
-              (Inst, To_Uns64 (Read_Discrete (Left)), Right, Expr);
+              (Inst, To_Uns64 (Read_Discrete (Param1)), Param2, Expr);
 
          when Iir_Predefined_Ieee_Numeric_Std_Div_Sgn_Sgn =>
-            return Div_Sgn_Sgn (Inst, Left, Right, Expr);
+            return Div_Sgn_Sgn (Inst, Param1, Param2, Expr);
          when Iir_Predefined_Ieee_Numeric_Std_Div_Int_Sgn =>
-            return Div_Int_Sgn (Inst, Read_Discrete (Left), Right, Expr);
+            return Div_Int_Sgn (Inst, Read_Discrete (Param1), Param2, Expr);
          when Iir_Predefined_Ieee_Numeric_Std_Div_Sgn_Int =>
-            return Div_Sgn_Int (Inst, Left, Read_Discrete (Right), Expr);
+            return Div_Sgn_Int (Inst, Param1, Read_Discrete (Param2), Expr);
 
          when Iir_Predefined_Ieee_Numeric_Std_Rem_Uns_Uns
             | Iir_Predefined_Ieee_Numeric_Std_Mod_Uns_Uns =>
-            return Rem_Uns_Uns (Inst, Left, Right, Expr);
+            return Rem_Uns_Uns (Inst, Param1, Param2, Expr);
          when Iir_Predefined_Ieee_Numeric_Std_Rem_Uns_Nat
             | Iir_Predefined_Ieee_Numeric_Std_Mod_Uns_Nat =>
             return Rem_Uns_Nat
-              (Inst, Left, To_Uns64 (Read_Discrete (Right)), Expr);
+              (Inst, Param1, To_Uns64 (Read_Discrete (Param2)), Expr);
          when Iir_Predefined_Ieee_Numeric_Std_Rem_Nat_Uns
             | Iir_Predefined_Ieee_Numeric_Std_Mod_Nat_Uns =>
             return Rem_Nat_Uns
-              (Inst, To_Uns64 (Read_Discrete (Left)), Right, Expr);
+              (Inst, To_Uns64 (Read_Discrete (Param1)), Param2, Expr);
 
          when Iir_Predefined_Ieee_Numeric_Std_Rem_Sgn_Sgn =>
-            return Rem_Sgn_Sgn (Inst, Left, Right, Expr);
+            return Rem_Sgn_Sgn (Inst, Param1, Param2, Expr);
          when Iir_Predefined_Ieee_Numeric_Std_Rem_Int_Sgn =>
-            return Rem_Int_Sgn (Inst, Read_Discrete (Left), Right, Expr);
+            return Rem_Int_Sgn (Inst, Read_Discrete (Param1), Param2, Expr);
          when Iir_Predefined_Ieee_Numeric_Std_Rem_Sgn_Int =>
-            return Rem_Sgn_Int (Inst, Left, Read_Discrete (Right), Expr);
+            return Rem_Sgn_Int (Inst, Param1, Read_Discrete (Param2), Expr);
 
          when Iir_Predefined_Ieee_Numeric_Std_Mod_Sgn_Sgn =>
-            return Mod_Sgn_Sgn (Inst, Left, Right, Expr);
+            return Mod_Sgn_Sgn (Inst, Param1, Param2, Expr);
          when Iir_Predefined_Ieee_Numeric_Std_Mod_Int_Sgn =>
-            return Mod_Int_Sgn (Inst, Read_Discrete (Left), Right, Expr);
+            return Mod_Int_Sgn (Inst, Read_Discrete (Param1), Param2, Expr);
          when Iir_Predefined_Ieee_Numeric_Std_Mod_Sgn_Int =>
-            return Mod_Sgn_Int (Inst, Left, Read_Discrete (Right), Expr);
+            return Mod_Sgn_Int (Inst, Param1, Read_Discrete (Param2), Expr);
 
          when Iir_Predefined_Ieee_Numeric_Std_Srl_Uns_Int
            |  Iir_Predefined_Ieee_Numeric_Std_Srl_Sgn_Int =>
             declare
                Amt : Int64;
             begin
-               Amt := Read_Discrete (Right);
+               Amt := Read_Discrete (Param2);
                if Amt >= 0 then
-                  return Shift_Vec (Left, Uns32 (Amt), True, False);
+                  return Shift_Vec (Param1, Uns32 (Amt), True, False);
                else
-                  return Shift_Vec (Left, Uns32 (-Amt), False, False);
+                  return Shift_Vec (Param1, Uns32 (-Amt), False, False);
                end if;
             end;
          when Iir_Predefined_Ieee_Numeric_Std_Sll_Uns_Int
@@ -1757,11 +2361,11 @@ package body Synth.Vhdl_Eval is
             declare
                Amt : Int64;
             begin
-               Amt := Read_Discrete (Right);
+               Amt := Read_Discrete (Param2);
                if Amt >= 0 then
-                  return Shift_Vec (Left, Uns32 (Amt), False, False);
+                  return Shift_Vec (Param1, Uns32 (Amt), False, False);
                else
-                  return Shift_Vec (Left, Uns32 (-Amt), True, False);
+                  return Shift_Vec (Param1, Uns32 (-Amt), True, False);
                end if;
             end;
 
@@ -1769,50 +2373,50 @@ package body Synth.Vhdl_Eval is
             declare
                Res : Std_Ulogic;
             begin
-               Res := Match_Eq_Vec_Vec (Left, Right, False, +Expr);
+               Res := Match_Eq_Vec_Vec (Param1, Param2, False, +Expr);
                return Create_Memory_U8 (Std_Ulogic'Pos (Res), Res_Typ);
             end;
          when Iir_Predefined_Ieee_Numeric_Std_Match_Ne_Uns_Uns =>
             declare
                Res : Std_Ulogic;
             begin
-               Res := Match_Eq_Vec_Vec (Left, Right, False, +Expr);
+               Res := Match_Eq_Vec_Vec (Param1, Param2, False, +Expr);
                Res := Not_Table (Res);
                return Create_Memory_U8 (Std_Ulogic'Pos (Res), Res_Typ);
             end;
 
          when Iir_Predefined_Ieee_Numeric_Std_Match_Lt_Uns_Uns =>
-            return Match_Cmp_Vec_Vec (Left, Right, Map_Lt, False, +Expr);
+            return Match_Cmp_Vec_Vec (Param1, Param2, Map_Lt, False, +Expr);
          when Iir_Predefined_Ieee_Numeric_Std_Match_Lt_Sgn_Sgn =>
-            return Match_Cmp_Vec_Vec (Left, Right, Map_Lt, True, +Expr);
+            return Match_Cmp_Vec_Vec (Param1, Param2, Map_Lt, True, +Expr);
 
          when Iir_Predefined_Ieee_Numeric_Std_Match_Le_Uns_Uns =>
-            return Match_Cmp_Vec_Vec (Left, Right, Map_Le, False, +Expr);
+            return Match_Cmp_Vec_Vec (Param1, Param2, Map_Le, False, +Expr);
          when Iir_Predefined_Ieee_Numeric_Std_Match_Le_Sgn_Sgn =>
-            return Match_Cmp_Vec_Vec (Left, Right, Map_Le, True, +Expr);
+            return Match_Cmp_Vec_Vec (Param1, Param2, Map_Le, True, +Expr);
 
          when Iir_Predefined_Ieee_Numeric_Std_Match_Gt_Uns_Uns =>
-            return Match_Cmp_Vec_Vec (Left, Right, Map_Gt, False, +Expr);
+            return Match_Cmp_Vec_Vec (Param1, Param2, Map_Gt, False, +Expr);
          when Iir_Predefined_Ieee_Numeric_Std_Match_Gt_Sgn_Sgn =>
-            return Match_Cmp_Vec_Vec (Left, Right, Map_Gt, True, +Expr);
+            return Match_Cmp_Vec_Vec (Param1, Param2, Map_Gt, True, +Expr);
 
          when Iir_Predefined_Ieee_Numeric_Std_Match_Ge_Uns_Uns =>
-            return Match_Cmp_Vec_Vec (Left, Right, Map_Ge, False, +Expr);
+            return Match_Cmp_Vec_Vec (Param1, Param2, Map_Ge, False, +Expr);
          when Iir_Predefined_Ieee_Numeric_Std_Match_Ge_Sgn_Sgn =>
-            return Match_Cmp_Vec_Vec (Left, Right, Map_Ge, True, +Expr);
+            return Match_Cmp_Vec_Vec (Param1, Param2, Map_Ge, True, +Expr);
 
          when Iir_Predefined_Ieee_Numeric_Std_Match_Eq_Sgn_Sgn =>
             declare
                Res : Std_Ulogic;
             begin
-               Res := Match_Eq_Vec_Vec (Left, Right, True, +Expr);
+               Res := Match_Eq_Vec_Vec (Param1, Param2, True, +Expr);
                return Create_Memory_U8 (Std_Ulogic'Pos (Res), Res_Typ);
             end;
          when Iir_Predefined_Ieee_Numeric_Std_Match_Ne_Sgn_Sgn =>
             declare
                Res : Std_Ulogic;
             begin
-               Res := Match_Eq_Vec_Vec (Left, Right, True, +Expr);
+               Res := Match_Eq_Vec_Vec (Param1, Param2, True, +Expr);
                Res := Not_Table (Res);
                return Create_Memory_U8 (Std_Ulogic'Pos (Res), Res_Typ);
             end;
@@ -1823,7 +2427,7 @@ package body Synth.Vhdl_Eval is
                pragma Import (C, Pow);
             begin
                return Create_Memory_Fp64
-                 (Pow (Read_Fp64 (Left), Read_Fp64 (Right)), Res_Typ);
+                 (Pow (Read_Fp64 (Param1), Read_Fp64 (Param2)), Res_Typ);
             end;
 
          when Iir_Predefined_Ieee_Math_Real_Mod =>
@@ -1832,634 +2436,9 @@ package body Synth.Vhdl_Eval is
                pragma Import (C, Fmod);
             begin
                return Create_Memory_Fp64
-                 (Fmod (Read_Fp64 (Left), Read_Fp64 (Right)), Res_Typ);
-            end;
-
-         when others =>
-            Error_Msg_Synth
-              (Inst, Expr, "eval_static_dyadic_predefined: unhandled "
-                 & Iir_Predefined_Functions'Image (Def));
-            return Null_Memtyp;
-      end case;
-   end Eval_Static_Dyadic_Predefined;
-
-   function Eval_Vector_Monadic (Vec : Memtyp; Op : Table_1d) return Memtyp
-   is
-      Len : constant Iir_Index32 := Vec_Length (Vec.Typ);
-      Res : Memtyp;
-   begin
-      Res := Create_Memory (Create_Res_Bound (Vec.Typ));
-      for I in 1 .. Uns32 (Len) loop
-         declare
-            V : constant Std_Ulogic := Read_Std_Logic (Vec.Mem, I - 1);
-         begin
-            Write_Std_Logic (Res.Mem, I - 1, Op (V));
-         end;
-      end loop;
-      return Res;
-   end Eval_Vector_Monadic;
-
-   function Eval_Vector_Reduce (Init : Std_Ulogic;
-                                Vec : Memtyp;
-                                Op : Table_2d;
-                                Neg : Boolean) return Memtyp
-   is
-      El_Typ : constant Type_Acc := Vec.Typ.Arr_El;
-      Res : Std_Ulogic;
-   begin
-      Res := Init;
-      for I in 1 .. Uns32 (Vec_Length (Vec.Typ)) loop
-         declare
-            V : constant Std_Ulogic := Read_Std_Logic (Vec.Mem, I - 1);
-         begin
-            Res := Op (Res, V);
-         end;
-      end loop;
-
-      if Neg then
-         Res := Not_Table (Res);
-      end if;
-
-      return Create_Memory_U8 (Std_Ulogic'Pos (Res), El_Typ);
-   end Eval_Vector_Reduce;
-
-   function Eval_TF_Vector_Monadic (Vec : Memtyp) return Memtyp
-   is
-      Len : constant Iir_Index32 := Vec_Length (Vec.Typ);
-      Res : Memtyp;
-   begin
-      Res := Create_Memory (Create_Res_Bound (Vec.Typ));
-      for I in 1 .. Uns32 (Len) loop
-         declare
-            V : constant Boolean :=
-              Boolean'Val (Read_U8 (Vec.Mem + Size_Type (I - 1)));
-         begin
-            Write_U8 (Res.Mem + Size_Type (I - 1), Boolean'Pos (not V));
-         end;
-      end loop;
-      return Res;
-   end Eval_TF_Vector_Monadic;
-
-   function Eval_TF_Vector_Reduce (Init : Boolean;
-                                   Neg : Boolean;
-                                   Vec : Memtyp;
-                                   Op : Tf_Table_2d) return Memtyp
-   is
-      El_Typ : constant Type_Acc := Vec.Typ.Arr_El;
-      Res : Boolean;
-   begin
-      Res := Init;
-      for I in 1 .. Size_Type (Vec.Typ.Abound.Len) loop
-         declare
-            V : constant Boolean := Boolean'Val (Read_U8 (Vec.Mem + (I - 1)));
-         begin
-            Res := Op (Res, V);
-         end;
-      end loop;
-
-      return Create_Memory_U8 (Boolean'Pos (Res xor Neg), El_Typ);
-   end Eval_TF_Vector_Reduce;
-
-   function Eval_Vector_Maximum (Vec : Memtyp) return Memtyp
-   is
-      Etyp : constant Type_Acc := Vec.Typ.Arr_El;
-      Len : constant Uns32 := Vec.Typ.Abound.Len;
-   begin
-      case Etyp.Kind is
-         when Type_Logic
-           | Type_Bit
-           | Type_Discrete =>
-            declare
-               Res : Int64;
-               V : Int64;
-            begin
-               case Etyp.Drange.Dir is
-                  when Dir_To =>
-                     Res := Etyp.Drange.Left;
-                  when Dir_Downto =>
-                     Res := Etyp.Drange.Right;
-               end case;
-
-               for I in 1 .. Len loop
-                  V := Read_Discrete
-                    (Vec.Mem + Size_Type (I - 1) * Etyp.Sz, Etyp);
-                  if V > Res then
-                     Res := V;
-                  end if;
-               end loop;
-               return Create_Memory_Discrete (Res, Etyp);
-            end;
-         when Type_Float =>
-            declare
-               Res : Fp64;
-               V : Fp64;
-            begin
-               case Etyp.Frange.Dir is
-                  when Dir_To =>
-                     Res := Etyp.Frange.Left;
-                  when Dir_Downto =>
-                     Res := Etyp.Frange.Right;
-               end case;
-
-               for I in 1 .. Len loop
-                  V := Read_Fp64
-                    (Vec.Mem + Size_Type (I - 1) * Etyp.Sz);
-                  if V > Res then
-                     Res := V;
-                  end if;
-               end loop;
-               return Create_Memory_Fp64 (Res, Etyp);
-            end;
-         when others =>
-            raise Internal_Error;
-      end case;
-   end Eval_Vector_Maximum;
-
-   function Eval_Vector_Minimum (Vec : Memtyp) return Memtyp
-   is
-      Etyp : constant Type_Acc := Vec.Typ.Arr_El;
-      Len : constant Uns32 := Vec.Typ.Abound.Len;
-   begin
-      case Etyp.Kind is
-         when Type_Logic
-           | Type_Bit
-           | Type_Discrete =>
-            declare
-               Res : Int64;
-               V : Int64;
-            begin
-               case Etyp.Drange.Dir is
-                  when Dir_To =>
-                     Res := Etyp.Drange.Right;
-                  when Dir_Downto =>
-                     Res := Etyp.Drange.Left;
-               end case;
-
-               for I in 1 .. Len loop
-                  V := Read_Discrete
-                    (Vec.Mem + Size_Type (I - 1) * Etyp.Sz, Etyp);
-                  if V < Res then
-                     Res := V;
-                  end if;
-               end loop;
-               return Create_Memory_Discrete (Res, Etyp);
-            end;
-         when Type_Float =>
-            declare
-               Res : Fp64;
-               V : Fp64;
-            begin
-               case Etyp.Frange.Dir is
-                  when Dir_To =>
-                     Res := Etyp.Frange.Right;
-                  when Dir_Downto =>
-                     Res := Etyp.Frange.Left;
-               end case;
-
-               for I in 1 .. Len loop
-                  V := Read_Fp64
-                    (Vec.Mem + Size_Type (I - 1) * Etyp.Sz);
-                  if V < Res then
-                     Res := V;
-                  end if;
-               end loop;
-               return Create_Memory_Fp64 (Res, Etyp);
-            end;
-         when others =>
-            raise Internal_Error;
-      end case;
-   end Eval_Vector_Minimum;
-
-   function Eval_Static_Monadic_Predefined (Inst : Synth_Instance_Acc;
-                                            Imp : Node;
-                                            Operand : Memtyp;
-                                            Expr : Node) return Memtyp
-   is
-      Def : constant Iir_Predefined_Functions :=
-        Get_Implicit_Definition (Imp);
-   begin
-      case Def is
-         when Iir_Predefined_Boolean_Not
-           | Iir_Predefined_Bit_Not =>
-            return Create_Memory_U8 (1 - Read_U8 (Operand), Operand.Typ);
-
-         when Iir_Predefined_Bit_Condition =>
-            return Create_Memory_U8 (Read_U8 (Operand), Operand.Typ);
-
-         when Iir_Predefined_Integer_Negation
-           | Iir_Predefined_Physical_Negation =>
-            return Create_Memory_Discrete
-              (-Read_Discrete (Operand), Operand.Typ);
-         when Iir_Predefined_Integer_Absolute
-           | Iir_Predefined_Physical_Absolute =>
-            return Create_Memory_Discrete
-              (abs Read_Discrete (Operand), Operand.Typ);
-         when Iir_Predefined_Integer_Identity
-           | Iir_Predefined_Physical_Identity =>
-            return Operand;
-
-         when Iir_Predefined_Floating_Negation =>
-            return Create_Memory_Fp64 (-Read_Fp64 (Operand), Operand.Typ);
-         when Iir_Predefined_Floating_Identity =>
-            return Operand;
-         when Iir_Predefined_Floating_Absolute =>
-            return Create_Memory_Fp64 (abs Read_Fp64 (Operand), Operand.Typ);
-
-         when Iir_Predefined_Vector_Maximum =>
-            return Eval_Vector_Maximum (Operand);
-         when Iir_Predefined_Vector_Minimum =>
-            return Eval_Vector_Minimum (Operand);
-
-         when Iir_Predefined_TF_Array_Not =>
-            return Eval_TF_Vector_Monadic (Operand);
-
-         when Iir_Predefined_TF_Reduction_Or =>
-            return Eval_TF_Vector_Reduce (False, False, Operand, Tf_2d_Or);
-         when Iir_Predefined_TF_Reduction_And =>
-            return Eval_TF_Vector_Reduce (True, False, Operand, Tf_2d_And);
-         when Iir_Predefined_TF_Reduction_Xor =>
-            return Eval_TF_Vector_Reduce (False, False, Operand, Tf_2d_Xor);
-         when Iir_Predefined_TF_Reduction_Nor =>
-            return Eval_TF_Vector_Reduce (False, True, Operand, Tf_2d_Or);
-         when Iir_Predefined_TF_Reduction_Nand =>
-            return Eval_TF_Vector_Reduce (True, True, Operand, Tf_2d_And);
-         when Iir_Predefined_TF_Reduction_Xnor =>
-            return Eval_TF_Vector_Reduce (False, True, Operand, Tf_2d_Xor);
-
-         when Iir_Predefined_Ieee_1164_Condition_Operator =>
-            --  Constant std_logic: need to convert.
-            declare
-               Val : Uns32;
-               Zx : Uns32;
-            begin
-               From_Std_Logic (Int64 (Read_U8 (Operand)), Val, Zx);
-               return Create_Memory_U8
-                 (Boolean'Pos (Val = 1 and Zx = 0), Boolean_Type);
+                 (Fmod (Read_Fp64 (Param1), Read_Fp64 (Param2)), Res_Typ);
             end;
 
-         when Iir_Predefined_Ieee_Numeric_Std_Neg_Sgn =>
-            return Neg_Vec (Operand, +Expr);
-         when Iir_Predefined_Ieee_Numeric_Std_Abs_Sgn =>
-            return Abs_Vec (Operand, +Expr);
-
-         when Iir_Predefined_Ieee_1164_Vector_Not
-           | Iir_Predefined_Ieee_Numeric_Std_Not_Uns
-           | Iir_Predefined_Ieee_Numeric_Std_Not_Sgn =>
-            return Eval_Vector_Monadic (Operand, Not_Table);
-
-         when Iir_Predefined_Ieee_1164_Scalar_Not =>
-            return Create_Memory_U8
-              (Std_Ulogic'Pos (Not_Table (Read_Std_Logic (Operand.Mem, 0))),
-               Operand.Typ);
-
-         when Iir_Predefined_Ieee_1164_And_Suv
-            | Iir_Predefined_Ieee_Numeric_Std_And_Uns
-            | Iir_Predefined_Ieee_Numeric_Std_And_Sgn =>
-            return Eval_Vector_Reduce ('1', Operand, And_Table, False);
-         when Iir_Predefined_Ieee_1164_Nand_Suv
-            | Iir_Predefined_Ieee_Numeric_Std_Nand_Uns
-            | Iir_Predefined_Ieee_Numeric_Std_Nand_Sgn =>
-            return Eval_Vector_Reduce ('1', Operand, And_Table, True);
-
-         when Iir_Predefined_Ieee_1164_Or_Suv
-            | Iir_Predefined_Ieee_Numeric_Std_Or_Uns
-            | Iir_Predefined_Ieee_Numeric_Std_Or_Sgn =>
-            return Eval_Vector_Reduce ('0', Operand, Or_Table, False);
-         when Iir_Predefined_Ieee_1164_Nor_Suv
-            | Iir_Predefined_Ieee_Numeric_Std_Nor_Uns
-            | Iir_Predefined_Ieee_Numeric_Std_Nor_Sgn =>
-            return Eval_Vector_Reduce ('0', Operand, Or_Table, True);
-
-         when Iir_Predefined_Ieee_1164_Xor_Suv
-            | Iir_Predefined_Ieee_Numeric_Std_Xor_Uns
-            | Iir_Predefined_Ieee_Numeric_Std_Xor_Sgn =>
-            return Eval_Vector_Reduce ('0', Operand, Xor_Table, False);
-         when Iir_Predefined_Ieee_1164_Xnor_Suv
-            | Iir_Predefined_Ieee_Numeric_Std_Xnor_Uns
-            | Iir_Predefined_Ieee_Numeric_Std_Xnor_Sgn =>
-            return Eval_Vector_Reduce ('0', Operand, Xor_Table, True);
-
-         when Iir_Predefined_Ieee_Std_Logic_Arith_Id_Uns_Uns
-            | Iir_Predefined_Ieee_Std_Logic_Arith_Id_Uns_Slv
-            | Iir_Predefined_Ieee_Std_Logic_Arith_Id_Sgn_Sgn
-            | Iir_Predefined_Ieee_Std_Logic_Arith_Id_Sgn_Slv
-            | Iir_Predefined_Ieee_Std_Logic_Unsigned_Id_Slv
-            | Iir_Predefined_Ieee_Std_Logic_Signed_Id_Slv =>
-            return Operand;
-
-         when Iir_Predefined_Ieee_Std_Logic_Arith_Neg_Sgn_Sgn
-            | Iir_Predefined_Ieee_Std_Logic_Arith_Neg_Sgn_Slv
-            | Iir_Predefined_Ieee_Std_Logic_Signed_Neg_Slv =>
-            return Neg_Sgn_Sgn (Operand, +Expr);
-
-         when Iir_Predefined_Ieee_Std_Logic_Arith_Abs_Sgn_Sgn
-            | Iir_Predefined_Ieee_Std_Logic_Arith_Abs_Sgn_Slv
-            | Iir_Predefined_Ieee_Std_Logic_Signed_Abs_Slv =>
-            return Abs_Sgn_Sgn (Operand, +Expr);
-
-         when others =>
-            Error_Msg_Synth
-              (Inst, Expr, "eval_static_monadic_predefined: unhandled "
-                 & Iir_Predefined_Functions'Image (Def));
-            raise Internal_Error;
-      end case;
-   end Eval_Static_Monadic_Predefined;
-
-   function Eval_To_Log_Vector (Arg : Uns64; Sz : Int64; Res_Type : Type_Acc)
-                               return Memtyp
-   is
-      Len : constant Iir_Index32 := Iir_Index32 (Sz);
-      El_Type : constant Type_Acc := Get_Array_Element (Res_Type);
-      Res : Memtyp;
-      Bnd : Type_Acc;
-      B : Uns64;
-   begin
-      Bnd := Create_Vec_Type_By_Length (Width (Len), El_Type);
-      Res := Create_Memory (Bnd);
-      for I in 1 .. Len loop
-         B := Shift_Right_Arithmetic (Arg, Natural (I - 1)) and 1;
-         Write_Std_Logic (Res.Mem, Uns32 (Len - I),
-                          Std_Ulogic'Val (Std_Logic_0_Pos + B));
-      end loop;
-      return Res;
-   end Eval_To_Log_Vector;
-
-   function Eval_To_Bit_Vector (Arg : Uns64; Sz : Int64; Res_Type : Type_Acc)
-                               return Memtyp
-   is
-      Len : constant Size_Type := Size_Type (Sz);
-      El_Type : constant Type_Acc := Get_Array_Element (Res_Type);
-      Res : Memtyp;
-      Bnd : Type_Acc;
-      B : Uns64;
-   begin
-      Bnd := Create_Vec_Type_By_Length (Width (Sz), El_Type);
-      Res := Create_Memory (Bnd);
-      for I in 1 .. Len loop
-         B := Shift_Right_Arithmetic (Arg, Natural (I - 1)) and 1;
-         Write_U8 (Res.Mem + (Len - I), Ghdl_U8 (B));
-      end loop;
-      return Res;
-   end Eval_To_Bit_Vector;
-
-   function Eval_Unsigned_To_Integer (Arg : Memtyp; Loc : Node) return Int64
-   is
-      Res : Uns64;
-      V : Std_Ulogic;
-   begin
-      Res := 0;
-      for I in 1 .. Vec_Length (Arg.Typ) loop
-         V := Std_Ulogic'Val (Read_U8 (Arg.Mem + Size_Type (I - 1)));
-         case To_X01 (V) is
-            when '0' =>
-               Res := Res * 2;
-            when '1' =>
-               Res := Res * 2 + 1;
-            when 'X' =>
-               Warning_Msg_Synth
-                 (+Loc, "metavalue detected, returning 0");
-               Res := 0;
-               exit;
-         end case;
-      end loop;
-      return To_Int64 (Res);
-   end Eval_Unsigned_To_Integer;
-
-   function Eval_Signed_To_Integer (Arg : Memtyp; Loc : Node) return Int64
-   is
-      Len : constant Iir_Index32 := Vec_Length (Arg.Typ);
-      Res : Uns64;
-      E : Std_Ulogic;
-   begin
-      if Len = 0 then
-         Warning_Msg_Synth
-           (+Loc, "numeric_std.to_integer: null detected, returning 0");
-         return 0;
-      end if;
-
-      E := Std_Ulogic'Val (Read_U8 (Arg.Mem));
-      case To_X01 (E) is
-         when '0' =>
-            Res := 0;
-         when '1' =>
-            Res := not 0;
-         when 'X' =>
-            Warning_Msg_Synth (+Loc, "metavalue detected, returning 0");
-            return 0;
-      end case;
-      for I in 2 .. Len loop
-         E := Std_Ulogic'Val (Read_U8 (Arg.Mem + Size_Type (I - 1)));
-         case To_X01 (E) is
-            when '0' =>
-               Res := Res * 2;
-            when '1' =>
-               Res := Res * 2 + 1;
-            when 'X' =>
-               Warning_Msg_Synth (+Loc, "metavalue detected, returning 0");
-               return 0;
-         end case;
-      end loop;
-      return To_Int64 (Res);
-   end Eval_Signed_To_Integer;
-
-   function Eval_Array_Char_To_String (Param : Memtyp;
-                                       Res_Typ : Type_Acc;
-                                       Imp : Node) return Memtyp
-   is
-      use Vhdl.Utils;
-      use Name_Table;
-      Len : constant Uns32 := Param.Typ.Abound.Len;
-      Elt : constant Type_Acc := Param.Typ.Arr_El;
-      Etype : constant Node := Get_Base_Type
-        (Get_Element_Subtype
-           (Get_Type (Get_Interface_Declaration_Chain (Imp))));
-      pragma Assert (Get_Kind (Etype) = Iir_Kind_Enumeration_Type_Definition);
-      Enums : constant Iir_Flist := Get_Enumeration_Literal_List (Etype);
-      Lit : Node;
-      Lit_Id : Name_Id;
-      Bnd : Bound_Type;
-      Res_St : Type_Acc;
-      Res : Memtyp;
-      V : Int64;
-   begin
-      Bnd := Elab.Vhdl_Types.Create_Bounds_From_Length
-        (Res_Typ.Uarr_Idx.Drange, Iir_Index32 (Len));
-      Res_St := Create_Onedimensional_Array_Subtype
-        (Res_Typ, Bnd, Res_Typ.Uarr_El);
-      Res := Create_Memory (Res_St);
-      for I in 1 .. Len loop
-         V := Read_Discrete (Param.Mem + Size_Type (I - 1) * Elt.Sz, Elt);
-         Lit := Get_Nth_Element (Enums, Natural (V));
-         Lit_Id := Get_Identifier (Lit);
-         pragma Assert (Is_Character (Lit_Id));
-         Write_U8 (Res.Mem + Size_Type (I - 1),
-                   Character'Pos (Get_Character (Lit_Id)));
-      end loop;
-      return Res;
-   end Eval_Array_Char_To_String;
-
-   function String_To_Memtyp (Str : String; Styp : Type_Acc) return Memtyp
-   is
-      Len : constant Natural := Str'Length;
-      Bnd : Bound_Type;
-      Typ : Type_Acc;
-      Res : Memtyp;
-   begin
-      Bnd := (Dir => Dir_To, Left => 1, Right => Int32 (Len),
-              Len => Uns32 (Len));
-      Typ := Create_Array_Type (Bnd, True, Styp.Uarr_El);
-
-      Res := Create_Memory (Typ);
-      for I in Str'Range loop
-         Write_U8 (Res.Mem + Size_Type (I - Str'First),
-                   Character'Pos (Str (I)));
-      end loop;
-      return Res;
-   end String_To_Memtyp;
-
-   function Eval_Enum_To_String (Param : Memtyp;
-                                 Res_Typ : Type_Acc;
-                                 Imp : Node) return Memtyp
-   is
-      use Vhdl.Utils;
-      use Name_Table;
-      Etype : constant Node := Get_Base_Type
-        (Get_Type (Get_Interface_Declaration_Chain (Imp)));
-      pragma Assert (Get_Kind (Etype) = Iir_Kind_Enumeration_Type_Definition);
-      Enums : constant Iir_Flist := Get_Enumeration_Literal_List (Etype);
-      Lit : Node;
-      Lit_Id : Name_Id;
-      V : Int64;
-      C : String (1 .. 1);
-   begin
-      V := Read_Discrete (Param.Mem, Param.Typ);
-      Lit := Get_Nth_Element (Enums, Natural (V));
-      Lit_Id := Get_Identifier (Lit);
-      if Is_Character (Lit_Id) then
-         C (1) := Get_Character (Lit_Id);
-         return String_To_Memtyp (C, Res_Typ);
-      else
-         return String_To_Memtyp (Image (Lit_Id), Res_Typ);
-      end if;
-   end Eval_Enum_To_String;
-
-   Hex_Chars : constant array (Natural range 0 .. 15) of Character :=
-     "0123456789ABCDEF";
-
-   function Eval_Bit_Vector_To_String (Val : Memtyp;
-                                       Res_Typ : Type_Acc;
-                                       Log_Base : Natural) return Memtyp
-   is
-      Base : constant Natural := 2 ** Log_Base;
-      Blen : constant Natural := Natural (Val.Typ.Abound.Len);
-      Str : String (1 .. (Blen + Log_Base - 1) / Log_Base);
-      Pos : Natural;
-      V : Natural;
-      N : Natural;
-   begin
-      V := 0;
-      N := 1;
-      Pos := Str'Last;
-      for I in 1 .. Blen loop
-         V := V + Natural (Read_U8 (Val.Mem + Size_Type (Blen - I))) * N;
-         N := N * 2;
-         if N = Base or else I = Blen then
-            Str (Pos) := Hex_Chars (V);
-            Pos := Pos - 1;
-            N := 1;
-            V := 0;
-         end if;
-      end loop;
-      return String_To_Memtyp (Str, Res_Typ);
-   end Eval_Bit_Vector_To_String;
-
-   function Eval_Logic_Vector_To_String (Val : Memtyp;
-                                         Res_Typ : Type_Acc;
-                                         Is_Signed : Boolean;
-                                         Log_Base : Natural) return Memtyp
-   is
-      Base : constant Natural := 2 ** Log_Base;
-      Blen : constant Uns32 := Val.Typ.Abound.Len;
-      Str : String (1 .. (Natural (Blen) + Log_Base - 1) / Log_Base);
-      Pos : Natural;
-      D : Std_Ulogic;
-      V : Natural;
-      N : Natural;
-      Has_X, Has_Z, Has_D : Boolean;
-   begin
-      V := 0;
-      N := 1;
-      Has_X := False;
-      Has_Z := False;
-      Has_D := False;
-      Pos := Str'Last;
-      for I in 1 .. Blen loop
-         D := Read_Std_Logic (Val.Mem, Blen - I);
-         case D is
-            when '0' | 'L' =>
-               Has_D := True;
-            when '1' | 'H' =>
-               Has_D := True;
-               V := V + N;
-            when 'Z' | 'W' =>
-               Has_Z := True;
-            when 'X' | 'U' | '-' =>
-               Has_X := True;
-         end case;
-         N := N * 2;
-         if N = Base or else I = Blen then
-            if Has_X or (Has_Z and Has_D) then
-               Str (Pos) := 'X';
-            elsif Has_Z then
-               Str (Pos) := 'Z';
-            else
-               if Is_Signed and N < Base and (D = '1' or D = 'H') then
-                  --  Sign extend.
-                  loop
-                     V := V + N;
-                     N := N * 2;
-                     exit when N = Base;
-                  end loop;
-               end if;
-               Str (Pos) := Hex_Chars (V);
-            end if;
-            Pos := Pos - 1;
-            N := 1;
-            V := 0;
-            Has_X := False;
-            Has_Z := False;
-            Has_D := False;
-         end if;
-      end loop;
-      return String_To_Memtyp (Str, Res_Typ);
-   end Eval_Logic_Vector_To_String;
-
-   function Eval_To_X01 (Val : Memtyp; Map : Table_1d) return Memtyp
-   is
-      Len : constant Uns32 := Val.Typ.Abound.Len;
-      Res : Memtyp;
-      B : Std_Ulogic;
-   begin
-      Res := Create_Memory (Create_Res_Bound (Val.Typ));
-      for I in 1 .. Len loop
-         B := Read_Std_Logic (Val.Mem, I - 1);
-         B := Map (B);
-         Write_Std_Logic (Res.Mem, I - 1, B);
-      end loop;
-      return Res;
-   end Eval_To_X01;
-
-   function Eval_Static_Predefined_Function_Call (Inst : Synth_Instance_Acc;
-                                                  Param1 : Memtyp;
-                                                  Param2 : Memtyp;
-                                                  Res_Typ : Type_Acc;
-                                                  Expr : Node) return Memtyp
-   is
-      Imp  : constant Node := Get_Implementation (Expr);
-      Def : constant Iir_Predefined_Functions :=
-        Get_Implicit_Definition (Imp);
-   begin
-      case Def is
          when Iir_Predefined_Physical_Minimum
            | Iir_Predefined_Integer_Minimum
            | Iir_Predefined_Enum_Minimum =>
diff --git a/src/synth/synth-vhdl_eval.ads b/src/synth/synth-vhdl_eval.ads
index 3c56ed3f6..c8c711422 100644
--- a/src/synth/synth-vhdl_eval.ads
+++ b/src/synth/synth-vhdl_eval.ads
@@ -24,17 +24,6 @@ with Vhdl.Nodes; use Vhdl.Nodes;
 package Synth.Vhdl_Eval is
    --  Note: INST is only used to report errors.
 
-   function Eval_Static_Dyadic_Predefined (Inst : Synth_Instance_Acc;
-                                           Imp : Node;
-                                           Res_Typ : Type_Acc;
-                                           Left : Memtyp;
-                                           Right : Memtyp;
-                                           Expr : Node) return Memtyp;
-   function Eval_Static_Monadic_Predefined (Inst : Synth_Instance_Acc;
-                                            Imp : Node;
-                                            Operand : Memtyp;
-                                            Expr : Node) return Memtyp;
-
    function Eval_Static_Predefined_Function_Call (Inst : Synth_Instance_Acc;
                                                   Param1 : Memtyp;
                                                   Param2 : Memtyp;
diff --git a/src/synth/synth-vhdl_oper.adb b/src/synth/synth-vhdl_oper.adb
index 35ba7661a..2ed35c79c 100644
--- a/src/synth/synth-vhdl_oper.adb
+++ b/src/synth/synth-vhdl_oper.adb
@@ -736,9 +736,9 @@ package body Synth.Vhdl_Oper is
         (Syn_Inst, Right, Right_Typ, False, Expr);
 
       if Is_Static_Val (Left.Val) and Is_Static_Val (Right.Val) then
-         Srec := Eval_Static_Dyadic_Predefined
-           (Syn_Inst, Imp, Expr_Typ,
-            Get_Value_Memtyp (Left), Get_Value_Memtyp (Right), Expr);
+         Srec := Eval_Static_Predefined_Function_Call
+           (Syn_Inst, Get_Value_Memtyp (Left), Get_Value_Memtyp (Right),
+            Expr_Typ, Expr);
          if Srec = Null_Memtyp then
             return No_Valtyp;
          end if;
@@ -1713,8 +1713,9 @@ package body Synth.Vhdl_Oper is
 
       if Is_Static_Val (Operand.Val) then
          return Create_Value_Memtyp
-           (Eval_Static_Monadic_Predefined
-              (Syn_Inst, Imp, Get_Value_Memtyp (Operand), Loc));
+           (Eval_Static_Predefined_Function_Call
+              (Syn_Inst, Get_Value_Memtyp (Operand), Null_Memtyp,
+                null, Loc));
       end if;
 
       case Def is
@@ -1932,26 +1933,24 @@ package body Synth.Vhdl_Oper is
    end Synth_Vec_Reduce_Monadic;
 
    function Synth_Dynamic_Predefined_Function_Call
-     (Subprg_Inst : Synth_Instance_Acc; Expr : Node) return Valtyp
+     (Subprg_Inst : Synth_Instance_Acc;
+      Imp : Node;
+      L, R : Valtyp;
+      Expr : Node) return Valtyp
    is
       Ctxt : constant Context_Acc := Get_Build (Subprg_Inst);
-      Imp  : constant Node := Get_Implementation (Expr);
       Def : constant Iir_Predefined_Functions :=
         Get_Implicit_Definition (Imp);
-      Inter_Chain : constant Node := Get_Interface_Declaration_Chain (Imp);
-      Param1 : Node;
-      Param2 : Node;
       Res_Typ : constant Type_Acc :=
         Get_Subtype_Object (Subprg_Inst, Get_Type (Imp));
 
-      --  Resize PARAM1 to PARAM2 bit according to IS_SIGNED.
+      --  Resize L to R bit according to IS_SIGNED.
       function Synth_Conv_Vector (Is_Signed : Boolean) return Valtyp
       is
-         Arg : constant Valtyp := Get_Value (Subprg_Inst, Param1);
          Size_Vt : Valtyp;
          Size : Width;
       begin
-         Size_Vt := Get_Value (Subprg_Inst, Param2);
+         Size_Vt := R;
          Strip_Const (Size_Vt);
          if not Is_Static (Size_Vt.Val) then
             Error_Msg_Synth
@@ -1960,27 +1959,9 @@ package body Synth.Vhdl_Oper is
             return No_Valtyp;
          end if;
          Size := Uns32 (Read_Discrete (Size_Vt));
-         return Synth_Resize (Ctxt, Arg, Size, Is_Signed, Expr);
+         return Synth_Resize (Ctxt, L, Size, Is_Signed, Expr);
       end Synth_Conv_Vector;
-
-      L : Valtyp;
-      R : Valtyp;
    begin
-      Param1 := Inter_Chain;
-      if Param1 /= Null_Node then
-         L := Get_Value (Subprg_Inst, Param1);
-         Param2 := Get_Chain (Inter_Chain);
-         if Param2 /= Null_Node then
-            R := Get_Value (Subprg_Inst, Param2);
-         else
-            R := No_Valtyp;
-         end if;
-      else
-         L := No_Valtyp;
-         R := No_Valtyp;
-         Param2 := Null_Node;
-      end if;
-
       case Def is
          when Iir_Predefined_Endfile =>
             declare
@@ -2320,7 +2301,28 @@ package body Synth.Vhdl_Oper is
                end if;
             end;
          else
-            Res := Synth_Dynamic_Predefined_Function_Call (Subprg_Inst, Expr);
+            declare
+               Inter : Node;
+               L, R : Valtyp;
+            begin
+               Inter := Inter_Chain;
+               if Inter /= Null_Node then
+                  L := Get_Value (Subprg_Inst, Inter);
+                  Inter := Get_Chain (Inter_Chain);
+                  if Inter /= Null_Node then
+                     R := Get_Value (Subprg_Inst, Inter);
+                     pragma Assert (Get_Chain (Inter) = Null_Node);
+                  else
+                     R := No_Valtyp;
+                  end if;
+               else
+                  L := No_Valtyp;
+                  R := No_Valtyp;
+               end if;
+
+               Res := Synth_Dynamic_Predefined_Function_Call
+                 (Subprg_Inst, Get_Implementation (Expr), L, R, Expr);
+            end;
          end if;
       end if;