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* synth: handle element in target aggregate. Fix #2279Tristan Gingold2022-12-221-3/+7
* synth: factorize code (Exec_Name_Subtype). Fix #2273Tristan Gingold2022-12-181-1/+1
* synth-vhdl_stmts: handle impure functions.Tristan Gingold2022-12-161-1/+8
* synth: avoid a crash on signal assignment in non-sensitized process.Tristan Gingold2022-11-141-2/+9
* Added id to warnings related to attributes. (#2242)cderrien2022-11-081-1/+5
* synth: extract elab-vhdl_utils from synth-vhdl_stmts.Tristan Gingold2022-10-181-142/+8
* synth-vhdl_stmts(synth_verification_unit): always set instance_pool.Tristan Gingold2022-10-131-1/+3
* simul: signal attributes in actualsTristan Gingold2022-10-061-2/+4
* simul: complete concurrent procedure callsTristan Gingold2022-10-061-0/+5
* synth: avoid crash on invalid hdl in psl. Fix #2204Tristan Gingold2022-10-031-4/+9
* synth: improve error recoveryTristan Gingold2022-10-021-0/+3
* synth-vhdl_stmts: handle passive process. Fix ghdl/ghdl-yosys-plugin#174Tristan Gingold2022-10-021-18/+204
* synth: factorize codeTristan Gingold2022-09-301-8/+1
* synth: handle guard signal in expressionsTristan Gingold2022-09-281-0/+1
* synth: handle null-range loopsTristan Gingold2022-09-281-14/+23
* synth: handle names in record aggregate targetsTristan Gingold2022-09-281-0/+12
* synth: handle array target aggregateTristan Gingold2022-09-271-2/+6
* synth: handle attributes in configurationsTristan Gingold2022-09-261-0/+1
* synth: rework error procedure, always pass the instanceTristan Gingold2022-09-251-21/+24
* synth-vhdl_stmts: fix missing newline in default assertion messagesTristan Gingold2022-09-251-3/+3
* synth: handle default expression for IN variables in assocsTristan Gingold2022-09-251-4/+10
* synth: handle selected names in targetsTristan Gingold2022-09-251-1/+2
* synth: handle individual subprogram associations for expressionsTristan Gingold2022-09-251-55/+61
* synth: rework association conversionsTristan Gingold2022-09-251-28/+59
* synth-vhdl_stmts: rework for subprogram associations (WIP)Tristan Gingold2022-09-251-57/+36
* synth-vhdl_stmts: support of individual paramater associations (WIP)Tristan Gingold2022-09-251-106/+236
* synth-vhdl_stmts: refactore synth_subprogram_associationsTristan Gingold2022-09-251-49/+52
* synth-vhdl_stmts: refactoreTristan Gingold2022-09-251-23/+32
* synth-vhdl_stmts: refactoringTristan Gingold2022-09-251-189/+208
* synth-vhdl_stmts: rework in progress of subprogram associationsTristan Gingold2022-09-251-108/+115
* synth: rework subprogram associations (WIP)Tristan Gingold2022-09-191-41/+81
* synth-vhdl_stmts: minor renamingTristan Gingold2022-09-181-5/+5
* synth: handle open variable associationTristan Gingold2022-09-171-22/+31
* synth: handle incomplete typesTristan Gingold2022-09-171-10/+11
* synth: preliminary work to factorize codeTristan Gingold2022-09-161-31/+49
* synth: improve handling of complex typesTristan Gingold2022-09-151-1/+1
* synth: handle vhdl-87 filesTristan Gingold2022-09-151-0/+6
* synth-vhdl_stmts: handle attribute names in expressionsTristan Gingold2022-09-141-1/+3
* simul: do not consider signal parameters as dynamic valuesTristan Gingold2022-09-121-1/+3
* synth: improve handling of top-level interfaces subtypeTristan Gingold2022-09-111-3/+4
* synth: initialize out parameters of proceduresTristan Gingold2022-09-111-2/+9
* synth: fix and add checks for memory management.Tristan Gingold2022-09-101-45/+136
* simul: add support for protected objectsTristan Gingold2022-09-081-10/+75
* elab-vhdl_values: factorize codeTristan Gingold2022-09-071-2/+2
* synth-vhdl_stmts: fix handling of copyback parametersTristan Gingold2022-09-071-6/+19
* simul: add an hook to display report/assert messageTristan Gingold2022-09-061-32/+68
* synth: use areapoolsTristan Gingold2022-09-021-14/+70
* synth: factorize code for tracing statements executionTristan Gingold2022-09-021-13/+2
* synth: factorize code for synth_subtype_conversionTristan Gingold2022-08-211-9/+8
* simul-vhdl_simul: add support for PSL directivesTristan Gingold2022-08-201-20/+16
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