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path: root/src/synth/synth-vhdl_stmts.adb
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* synth: support aggregate when target is a dynamic sliceTristan Gingold2023-04-191-1/+3
* synth: handle conditional variable assignment with no default.Tristan Gingold2023-04-141-2/+16
* synth_conditiona_signal_assignment: handle simple case directly.Tristan Gingold2023-03-141-46/+79
* synth: support selected signal assignmentTristan Gingold2023-03-091-0/+2
* synth-vhdl_stmts: handle unaffected in conditional variable assignmentsTristan Gingold2023-03-021-3/+11
* synth: handle unaffected in simple sequential signal assignment.Tristan Gingold2023-02-251-4/+9
* synth: preliminary work for PSL endpointsTristan Gingold2023-02-081-0/+17
* synth: use same layout for records in memory as translateTristan Gingold2023-02-081-7/+8
* simul: use same packing order for nets and for values.Tristan Gingold2023-01-301-1/+1
* synth: represent access types as pointers in memoryTristan Gingold2023-01-291-2/+2
* synth: add partial support of foreign subprogramsTristan Gingold2023-01-201-2/+3
* synth: emit an error message on foreign subprogram callsTristan Gingold2023-01-161-0/+11
* synth: handle invididual assoc with unbounded formalsTristan Gingold2023-01-161-6/+130
* synth: more refactoringTristan Gingold2023-01-141-13/+11
* synth: improve error propagation on slicesTristan Gingold2023-01-141-2/+6
* synth-vhdl_stmts: introduce synth_individual_formalTristan Gingold2023-01-141-18/+107
* synth-vhdl_stmts: refactoringTristan Gingold2023-01-141-103/+131
* synth: handle protected functions in conversion functionsTristan Gingold2023-01-121-6/+13
* synth: handle operator as conversion functionTristan Gingold2023-01-121-1/+13
* simul: improve assertion messages for pslTristan Gingold2023-01-111-23/+30
* synth: fix memory allocation in predefined function callsTristan Gingold2023-01-101-1/+3
* synth: handle indexes in arrays conversionTristan Gingold2023-01-101-8/+17
* synth: improve support of individual association for subprogramsTristan Gingold2023-01-091-1/+2
* synth-vhdl_stmts: handle indexes in image attributeTristan Gingold2023-01-091-5/+8
* synth: fix handling of formal slices in individual associationsTristan Gingold2023-01-091-2/+4
* synth: use same error message for null access as simulationTristan Gingold2023-01-061-1/+1
* synth: detect null access dereference, fix offset.Tristan Gingold2023-01-041-3/+12
* synth: check length of selector in case statementTristan Gingold2023-01-041-0/+4
* synth: fix handling of target aggregate in conditional variable assignmentTristan Gingold2023-01-041-3/+4
* synth: elaborate case generate statementsTristan Gingold2023-01-011-16/+18
* synth: add statement in context, adjust path/instance name attributesTristan Gingold2022-12-311-3/+4
* synth: add value_sig_val to handle individual signal associationsTristan Gingold2022-12-261-19/+15
* synth-vhdl_stmts(Aggregate_Array_Extract): fix offset for vector extractionTristan Gingold2022-12-261-1/+2
* synth: handle element in target aggregate. Fix #2279Tristan Gingold2022-12-221-3/+7
* synth: factorize code (Exec_Name_Subtype). Fix #2273Tristan Gingold2022-12-181-1/+1
* synth-vhdl_stmts: handle impure functions.Tristan Gingold2022-12-161-1/+8
* synth: avoid a crash on signal assignment in non-sensitized process.Tristan Gingold2022-11-141-2/+9
* Added id to warnings related to attributes. (#2242)cderrien2022-11-081-1/+5
* synth: extract elab-vhdl_utils from synth-vhdl_stmts.Tristan Gingold2022-10-181-142/+8
* synth-vhdl_stmts(synth_verification_unit): always set instance_pool.Tristan Gingold2022-10-131-1/+3
* simul: signal attributes in actualsTristan Gingold2022-10-061-2/+4
* simul: complete concurrent procedure callsTristan Gingold2022-10-061-0/+5
* synth: avoid crash on invalid hdl in psl. Fix #2204Tristan Gingold2022-10-031-4/+9
* synth: improve error recoveryTristan Gingold2022-10-021-0/+3
* synth-vhdl_stmts: handle passive process. Fix ghdl/ghdl-yosys-plugin#174Tristan Gingold2022-10-021-18/+204
* synth: factorize codeTristan Gingold2022-09-301-8/+1
* synth: handle guard signal in expressionsTristan Gingold2022-09-281-0/+1
* synth: handle null-range loopsTristan Gingold2022-09-281-14/+23
* synth: handle names in record aggregate targetsTristan Gingold2022-09-281-0/+12
* synth: handle array target aggregateTristan Gingold2022-09-271-2/+6
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