iCE40/ghdl - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	synth: handle some rotation and shifts. Fix #1077	Tristan Gingold	2020-01-30	1	-0/+6
*	synth: remove wbound field of bound_type.	Tristan Gingold	2020-01-13	1	-2/+1
*	synth: factorize code, move value2logvec to synth-expr.	Tristan Gingold	2019-11-28	1	-0/+21
*	synth: add debug_error.	Tristan Gingold	2019-11-22	1	-4/+0
*	synth: renames Is_Const to Is_Static.	Tristan Gingold	2019-11-13	1	-1/+1
*	synth: use synth.source for setting location.	Tristan Gingold	2019-10-09	1	-3/+0
*	synth: refactoring for memidx1.	Tristan Gingold	2019-10-02	1	-2/+7
*	synth: introduce memidx1	Tristan Gingold	2019-10-02	1	-1/+2
*	synth: improve support of arrays or arrays. Fix #955	Tristan Gingold	2019-10-01	1	-1/+4
*	synth: rework type for expression.	Tristan Gingold	2019-09-25	1	-1/+6
*	synth: preliminary work for subtype conversions on interfaces.	Tristan Gingold	2019-09-22	1	-3/+6
*	synth: fold addition on constant nets.	Tristan Gingold	2019-09-17	1	-0/+2
*	synth: remove get_width from synth-expr	Tristan Gingold	2019-09-12	1	-2/+0
*	synth: extract synth-oper from synth-expr	Tristan Gingold	2019-09-12	1	-1/+5
*	synth: rework partial assignments	Tristan Gingold	2019-08-27	1	-6/+3
*	synth: also extract edge in PSL expressions.	Tristan Gingold	2019-08-13	1	-0/+6
*	synth: handle subtype conversions.	Tristan Gingold	2019-08-05	1	-0/+5
*	synth: rework indexed names.	Tristan Gingold	2019-07-30	1	-1/+9
*	synth: add support for memories.	Tristan Gingold	2019-07-29	1	-2/+2
*	synth: preliminary support of dynamic indexing.	Tristan Gingold	2019-07-28	1	-8/+12
*	synth: save and display locations for instances.	Tristan Gingold	2019-07-25	1	-1/+5
*	synth: add concat_array function.	Tristan Gingold	2019-07-04	1	-0/+8
*	synth: add dyn_insert module.	Tristan Gingold	2019-07-01	1	-1/+1
*	synth: add syn_extract for dynamic slices.	Tristan Gingold	2019-06-28	1	-1/+5
*	synth: handle slice assignment.	Tristan Gingold	2019-06-25	1	-0/+5
*	synth: add insert gate.	Tristan Gingold	2019-06-24	1	-0/+5
*	synth: get rid of execution and elaboration.	Tristan Gingold	2019-06-19	1	-4/+14
*	synth-expr: use Node instead of Iir (renaming).	Tristan Gingold	2019-06-13	1	-2/+2
*	synth: add comments and refactoring.	Tristan Gingold	2019-06-07	1	-0/+1
*	vhdl: rename iirs to vhdl.nodes	Tristan Gingold	2019-05-05	1	-1/+1
*	synth: improve generation of aggregates.	Tristan Gingold	2019-04-16	1	-1/+1
*	Create the simul.ads package (for a namespace).	Tristan Gingold	2017-11-24	1	-1/+1
*	Add netlist generation infrastructure.	Tristan Gingold	2017-01-31	1	-0/+42