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| author | Tristan Gingold <tgingold@free.fr> | 2019-08-13 23:09:04 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2019-08-13 23:09:04 +0200 |
| commit | 3f3974481acdbaa36a607b9178f2ae751748020e (patch) | |
| tree | 38a69c207ee47deaf51cf971e7296ce5f4097bdf /src/synth/synth-expr.ads | |
| parent | de92555dc278dbb5799aaa386e1bd9b980ce0cbc (diff) | |
| download | ghdl-3f3974481acdbaa36a607b9178f2ae751748020e.tar.gz ghdl-3f3974481acdbaa36a607b9178f2ae751748020e.tar.bz2 ghdl-3f3974481acdbaa36a607b9178f2ae751748020e.zip | |
synth: also extract edge in PSL expressions.
Diffstat (limited to 'src/synth/synth-expr.ads')
| -rw-r--r-- | src/synth/synth-expr.ads | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/src/synth/synth-expr.ads b/src/synth/synth-expr.ads index be6daba0d..06b824fe2 100644 --- a/src/synth/synth-expr.ads +++ b/src/synth/synth-expr.ads @@ -42,6 +42,12 @@ package Synth.Expr is procedure To_Logic (Enum : Int64; Etype : Type_Acc; Val : out Uns32; Zx : out Uns32); + -- Try to match: clk'event and clk = X + -- or: clk = X and clk'event + -- where X is '0' or '1'. + function Synth_Clock_Edge + (Syn_Inst : Synth_Instance_Acc; Left, Right : Node) return Net; + function Bit_Extract (Val : Value_Acc; Off : Uns32; Loc : Node) return Value_Acc; |