aboutsummaryrefslogtreecommitdiffstats
path: root/src/synth/netlists-disp_verilog.adb
Commit message (Expand)AuthorAgeFilesLines
* synth: fix crash in disp_verilog. Fix #2234Tristan Gingold2022-10-291-3/+8
* netlists-disp_verilog(disp_const_log): fix output. Fix #2149Tristan Gingold2022-07-281-2/+2
* synth: Display dlatchTristan Gingold2022-07-141-0/+4
* netlists-disp_verilog: do not connect to null-range output. For #2113Tristan Gingold2022-07-081-41/+47
* netlists-disp_verilog: fix output for id_abs. For #2123Tristan Gingold2022-07-061-1/+2
* netlists-disp_verilog: handle Id_Abs. Fix #2113Tristan Gingold2022-07-041-1/+1
* netlists-disp_verilog: adjust, discard null signals. For #2113Tristan Gingold2022-06-281-1/+6
* netlists-disp_verilog: fix warningTristan Gingold2022-06-271-1/+2
* synth/netlists-disp_verilog: skip null input port. Fix #2113Tristan Gingold2022-06-271-15/+20
* synth: rework #2109 - remove null wiresTristan Gingold2022-06-271-3/+0
* synth/netlists-disp_verilog: adjust previous patch. For #2109Tristan Gingold2022-06-271-1/+2
* netlists-disp_verilog: do not display ports of width 0. Fix #2109Tristan Gingold2022-06-271-5/+19
* netlists-disp_verilog: do not display blackboxes. Fix #2092Tristan Gingold2022-06-131-0/+5
* netlists-disp_verilog: Use blocking assignments in non-clocked blocksAnton Blanchard2022-06-131-10/+10
* netlists-disp_verilog: output default value for pmux. Fix #2041Tristan Gingold2022-04-211-0/+1
* netlists-disp_verilog: fix disp_const_bitTristan Gingold2022-03-121-2/+2
* synth: put direction into port descTristan Gingold2021-11-171-8/+4
* synth: renaming to instance_attributes.Tristan Gingold2021-11-171-2/+2
* synth/netlists-disp_verilog: display port attributesTristan Gingold2021-11-171-18/+42
* netlists-disp_verilog: fix name for memory initializationTristan Gingold2021-09-281-3/+4
* netlists-disp_verilog: fix output of parameter assignments. Fix #1866Tristan Gingold2021-09-151-12/+12
* netlists-disp_verilog.adb: add 'parameter' before parameters declarationTristan Gingold2021-09-151-1/+1
* synth/netlists-disp_verilog: fix output of parameter values. For #1866Tristan Gingold2021-09-151-1/+13
* netlists-disp_verilog: handle initial value for idff and isignalTristan Gingold2021-08-281-8/+18
* netlists-disp_verilog: fix handling of unconnected portTristan Gingold2021-08-261-3/+1
* synth: reuse signal name while creating memories. Fix #1838Tristan Gingold2021-08-251-4/+4
* netlists-disp_verilog: fix display of constantsTristan Gingold2021-05-071-10/+20
* netlists-disp_verilog.adb: handle memidx, dyn_insert, dyn_extract.Tristan Gingold2021-05-041-74/+14
* synth: add verilog outputTristan Gingold2021-04-281-0/+1396