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authorTristan Gingold <tgingold@free.fr>2022-07-06 22:38:50 +0200
committerTristan Gingold <tgingold@free.fr>2022-07-06 22:38:50 +0200
commit774dcd646151328991440b7b7c2cbaf750dcc2b6 (patch)
tree47744f598b17094f4e5dbca9c1102faa0a533687 /src/synth/netlists-disp_verilog.adb
parent7783d1a1d87a8d8ae9c251d3a0091ff7fc728dd7 (diff)
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netlists-disp_verilog: fix output for id_abs. For #2123
Diffstat (limited to 'src/synth/netlists-disp_verilog.adb')
-rw-r--r--src/synth/netlists-disp_verilog.adb3
1 files changed, 2 insertions, 1 deletions
diff --git a/src/synth/netlists-disp_verilog.adb b/src/synth/netlists-disp_verilog.adb
index 7d1354403..950f6fd36 100644
--- a/src/synth/netlists-disp_verilog.adb
+++ b/src/synth/netlists-disp_verilog.adb
@@ -854,7 +854,8 @@ package body Netlists.Disp_Verilog is
when Id_Neg =>
Disp_Template (" assign \o0 = -\i0;" & NL, Inst);
when Id_Abs=>
- Disp_Template (" \o0 <= \si0 >= 0 ? \i0 : -\i0;" & NL, Inst);
+ Disp_Template (" assign \o0 = \si0 >= 0 ? \i0 : -\i0;" & NL,
+ Inst);
when Id_Extract =>
Disp_Template (" assign \o0 = ", Inst);
Disp_Extract (Inst);