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* simul: enable all debug features during elaborationTristan Gingold2023-01-102-5/+3
* synth: handle indexes in arrays conversionTristan Gingold2023-01-101-2/+2
* simul: handle inertial assignmentsTristan Gingold2023-01-101-2/+14
* synth-vhdl_aggr: optimize common aggregateTristan Gingold2023-01-101-6/+8
* synth: always create shared variablesTristan Gingold2023-01-091-21/+2
* simul: set assertion hook before elaborationTristan Gingold2023-01-091-3/+3
* simul-vhdl_simul: fix effective value writesTristan Gingold2023-01-091-1/+20
* simul: handle function calls in sensitivity compute.Tristan Gingold2023-01-091-0/+6
* simul: improve error recovery during elaborationTristan Gingold2023-01-091-3/+12
* simul: handle PSL coverTristan Gingold2023-01-092-3/+7
* simul: handle force/release signal assignmentsTristan Gingold2023-01-031-0/+174
* synth: introduce type_array_unboundedTristan Gingold2023-01-033-0/+4
* simul: skip psl default clock in declarationsTristan Gingold2023-01-031-0/+1
* synth: fix to_string for characterTristan Gingold2023-01-021-0/+3
* synth: elaborate case generate statementsTristan Gingold2023-01-011-1/+2
* simul: handle nested packagesTristan Gingold2023-01-011-1/+5
* synth: add statement in context, adjust path/instance name attributesTristan Gingold2022-12-311-1/+1
* simul: handle driving and driving_value attributesTristan Gingold2022-12-261-6/+39
* simul: handle transaction attributeTristan Gingold2022-12-262-3/+13
* simul: handle aggregate is guarded signal assignment targetTristan Gingold2022-12-261-7/+29
* vhdl-canon: handle unaffectedTristan Gingold2022-12-261-0/+5
* synth: add value_sig_val to handle individual signal associationsTristan Gingold2022-12-261-28/+166
* vhdl-sem_inst: add instantiate_interface_package_declarationTristan Gingold2022-12-181-0/+4
* vhdl: fix some compiler warningsTristan Gingold2022-11-082-4/+0
* simul: fix spurious error about multiple driversTristan Gingold2022-10-141-0/+2
* simul: handle delayed attributeTristan Gingold2022-10-142-6/+66
* simul: handle last_event and last_activeTristan Gingold2022-10-131-4/+98
* simul-vhdl_simul: keep default value of collapsed signalsTristan Gingold2022-10-131-1/+10
* simul-vhdl_elab: fix crash on association with implicit signalsTristan Gingold2022-10-131-1/+4
* simul: fix a crash due to missing strideTristan Gingold2022-10-131-5/+7
* simul: handle guarded concurrent assignmentsTristan Gingold2022-10-101-14/+32
* simul-vhdl_debug: handle state before elaborationTristan Gingold2022-10-101-0/+8
* simul: complete concurrent procedure callsTristan Gingold2022-10-061-27/+38
* simul: fix initial value of record signalsTristan Gingold2022-10-061-2/+2
* simul: recompute object alias offsetsTristan Gingold2022-10-061-1/+14
* simul: fix signal attribute or guard as actual in connectionsTristan Gingold2022-10-062-11/+15
* simul: improve debugger (display of signals value)Tristan Gingold2022-10-061-27/+26
* simul: handle suspendable procedure call from sensitized process.Tristan Gingold2022-10-052-3/+11
* simul: finalize empty proceduresTristan Gingold2022-10-011-9/+11
* simul: minor rewriteTristan Gingold2022-10-011-3/+2
* simul: finalize declarations of procedure callsTristan Gingold2022-10-011-0/+4
* simul: handle stable attributeTristan Gingold2022-09-302-5/+44
* synth: factorize codeTristan Gingold2022-09-301-0/+8
* simul: create disconnectionsTristan Gingold2022-09-301-1/+42
* simul: handle quiet attributeTristan Gingold2022-09-292-7/+72
* simul: factorize code, add sub_signal_typeTristan Gingold2022-09-294-92/+73
* simul: support guarded signal assignments (WIP)Tristan Gingold2022-09-291-8/+79
* synth: handle guard signal in debuggerTristan Gingold2022-09-281-56/+65
* simul: handle last_value attributeTristan Gingold2022-09-281-1/+23
* simul: fix handling of labels in next/exit statementsTristan Gingold2022-09-281-4/+13
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