| Commit message (Expand) | Author | Age | Files | Lines |
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| * | Workaround for Application class. | Patrick Lehmann | 2022-06-18 | 1 | -6/+2 |
| * | Bumped dependencies to support pyTooling ≥2.0. | Patrick Lehmann | 2022-06-18 | 2 | -3/+3 |
* | | vhdl-sem_lib: do not disable warnings for files in -c/-r | Tristan Gingold | 2022-06-19 | 1 | -1/+5 |
* | | testsuite/gna: add a test for #2066 | Tristan Gingold | 2022-06-19 | 3 | -0/+46 |
* | | trans-chap7: translate anonymous subtype of overflow literal. Fox #2066 | Tristan Gingold | 2022-06-19 | 1 | -2/+6 |
* | | vhdl-sem_expr: check expression index range for aggregate. Fix #2066 | Tristan Gingold | 2022-06-19 | 1 | -0/+25 |
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* | doc: document all warnings | Tristan Gingold | 2022-06-17 | 1 | -23/+122 |
* | testsuite/synth: add a test for #2099 | Tristan Gingold | 2022-06-16 | 2 | -0/+39 |
* | synth-vhdl_insts(synth_single_input_assoc): handle type conversion. | Tristan Gingold | 2022-06-16 | 2 | -4/+13 |
* | testsuite/gna: add a test for #2098 | Tristan Gingold | 2022-06-16 | 2 | -0/+167 |
* | vhdl-sem.adb(are_trees_equal): handle simple aggregate. | Tristan Gingold | 2022-06-16 | 1 | -14/+12 |
* | testsuite/gna: add a test for #2065 | Tristan Gingold | 2022-06-16 | 4 | -0/+742 |
* | vhdl/translate: handle inertial association in recursive instantiation | Tristan Gingold | 2022-06-16 | 2 | -2/+16 |
* | testsuite/gna: add a test for #2097 | Tristan Gingold | 2022-06-16 | 6 | -0/+209 |
* | vhdl-sem_names: handle element and subtype attributes for type conv. | Tristan Gingold | 2022-06-16 | 1 | -22/+26 |
* | vhdl-sem_expr: do not attribute element or subtype attributes as expr. | Tristan Gingold | 2022-06-16 | 1 | -0/+2 |
* | testsuite/gna: add a test for #2071 | Tristan Gingold | 2022-06-15 | 4 | -0/+111 |
* | vhdl: handle 'element in 'range. Fix #2071 | Tristan Gingold | 2022-06-15 | 2 | -23/+104 |
* | Add comments | Tristan Gingold | 2022-06-15 | 2 | -1/+2 |
* | testsuite/synth: add a test for #2093 | Tristan Gingold | 2022-06-15 | 3 | -1/+54 |
* | netlists-rename: handle handle signal instances. Fix #2093 | Tristan Gingold | 2022-06-15 | 3 | -2/+28 |
* | testsuite/synth: add a test for #2054 | Tristan Gingold | 2022-06-14 | 2 | -0/+27 |
* | src/synth: add netlists.rename to rename identifiers. Fix #2054 | Tristan Gingold | 2022-06-14 | 4 | -2/+132 |
* | testsuite/synth: add a test for #2092 | Tristan Gingold | 2022-06-13 | 2 | -0/+36 |
* | netlists-disp_verilog: do not display blackboxes. Fix #2092 | Tristan Gingold | 2022-06-13 | 1 | -0/+5 |
* | Merge pull request #2094 from antonblanchard/synth-verilog-blocking | tgingold | 2022-06-13 | 1 | -10/+10 |
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| * | netlists-disp_verilog: Use blocking assignments in non-clocked blocks | Anton Blanchard | 2022-06-13 | 1 | -10/+10 |
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* | testsuite/gna: add a test for #2091 | Tristan Gingold | 2022-06-12 | 3 | -0/+117 |
* | vhdl: add a parent field to protected_type_declaration. Fix #2091 | Tristan Gingold | 2022-06-12 | 3 | -265/+271 |
* | testsuite/synth: add a test. close #2080 | Tristan Gingold | 2022-06-12 | 3 | -0/+62 |
* | testsuite/synth: add a test for #2090 | Tristan Gingold | 2022-06-12 | 2 | -0/+70 |
* | synth-vhdl_insts: handle actual conversion function. Fix #2090 | Tristan Gingold | 2022-06-12 | 1 | -12/+38 |
* | testsuite/synth: add a test for #2089 | Tristan Gingold | 2022-06-12 | 2 | -0/+49 |
* | elab-vhdl_insts: eval inertial expressions to get the type. Fix #2089 | Tristan Gingold | 2022-06-12 | 2 | -7/+18 |
* | vhdl-nodes: add Inertial_Flag for association_element_by_expression | Tristan Gingold | 2022-06-12 | 7 | -387/+452 |
* | testsuite/synth: add tests for #2088 | Tristan Gingold | 2022-06-11 | 4 | -0/+117 |
* | elab-vhdl_types(Synth_Array_Attribute): handle dimension parameter | Tristan Gingold | 2022-06-11 | 1 | -1/+3 |
* | testsuite/synth: add a test for #2086 | Tristan Gingold | 2022-06-11 | 2 | -0/+35 |
* | synth-environment(Merge_Dyn_Insert): disable transformation. | Tristan Gingold | 2022-06-11 | 1 | -1/+3 |
* | netlists-memories: handle negation for In_Conjunction. Fix #2086 | Tristan Gingold | 2022-06-11 | 1 | -8/+3 |
* | synth-vhdl_eval: add support for more operations | Tristan Gingold | 2022-06-11 | 1 | -1/+10 |
* | vhdl: recognize ieee.math_real.sign, fix is_x recogn. | Tristan Gingold | 2022-06-11 | 9 | -217/+251 |
* | Merge pull request #2087 from Guiltybyte/support-non-glibc | tgingold | 2022-06-09 | 1 | -1/+1 |
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| * | deleted pragma messages | Guiltybyte | 2022-06-09 | 1 | -2/+0 |
| * | Only enable backtrace on linux if glibc is present | Guiltybyte | 2022-06-09 | 1 | -1/+3 |
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* | testsuite/synth: add a test for #2085 | Tristan Gingold | 2022-06-09 | 2 | -0/+35 |
* | elab-vhdl_types(Elab_Declaration_Type): rework to handle 'subtype | Tristan Gingold | 2022-06-09 | 7 | -30/+64 |
* | testsuite/synth: add a test for #2084 | Tristan Gingold | 2022-06-09 | 2 | -0/+23 |
* | vhdl-annotations: avoid a crash with subtype attribute in array. | Tristan Gingold | 2022-06-09 | 3 | -5/+16 |
* | testsuite/synth: add a test for #2083 | Tristan Gingold | 2022-06-08 | 2 | -0/+39 |