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authorTristan Gingold <tgingold@free.fr>2022-06-16 21:54:15 +0200
committerTristan Gingold <tgingold@free.fr>2022-06-16 21:54:15 +0200
commite4a9d487cc07abfc8abfeb1fa0dd955bcee0fd23 (patch)
tree36f0df8fdf8c5800f05240c3a81ce00d82718c9c
parentf300fd8ecf46c0e7af875040a8d40c63c3bb6886 (diff)
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testsuite/synth: add a test for #2099
-rw-r--r--testsuite/synth/issue2099/bug.vhdl32
-rwxr-xr-xtestsuite/synth/issue2099/testsuite.sh7
2 files changed, 39 insertions, 0 deletions
diff --git a/testsuite/synth/issue2099/bug.vhdl b/testsuite/synth/issue2099/bug.vhdl
new file mode 100644
index 000000000..0117c10da
--- /dev/null
+++ b/testsuite/synth/issue2099/bug.vhdl
@@ -0,0 +1,32 @@
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity bug is
+port(
+ clk : in std_ulogic
+);
+end entity;
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity ent is
+port(
+ data : in unsigned(15 downto 0)
+);
+end entity;
+
+architecture rtl of bug is
+
+ signal tmp : std_ulogic_vector(31 downto 0);
+
+begin
+ u0 : entity work.ent
+ port map(data => unsigned(tmp(15 downto 0)));
+end architecture;
+
+architecture rtl of ent is
+begin
+end architecture;
diff --git a/testsuite/synth/issue2099/testsuite.sh b/testsuite/synth/issue2099/testsuite.sh
new file mode 100755
index 000000000..6ec49749f
--- /dev/null
+++ b/testsuite/synth/issue2099/testsuite.sh
@@ -0,0 +1,7 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+synth_only bug
+
+echo "Test successful"