testsuite/gna: add a test for #2071

4 files changed, 111 insertions, 0 deletions

diff --git a/testsuite/gna/issue2071/repro.vhdl b/testsuite/gna/issue2071/repro.vhdl
new file mode 100644
index 000000000..aa6bcf1c0
--- /dev/null
+++ b/testsuite/gna/issue2071/repro.vhdl
@@ -0,0 +1,18 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity repro is
+end;
+
+architecture behav of repro is
+  type matrixType is array(natural range <>) of std_logic_vector;
+  signal matrix : matrixType(0 to 15)(7 downto 0);
+
+  -- Missing feature:
+  signal row1 : unsigned(matrix'element'range);
+
+  -- As a workaround:
+  signal row2 : unsigned(matrix(matrix'low)'range);
+begin
+end behav;
diff --git a/testsuite/gna/issue2071/repro2.vhdl b/testsuite/gna/issue2071/repro2.vhdl
new file mode 100644
index 000000000..f00671310
--- /dev/null
+++ b/testsuite/gna/issue2071/repro2.vhdl
@@ -0,0 +1,37 @@
+package TST_PKG is
+    type Indices_t is array (natural range <>) of bit_vector;
+
+    type Bus_t is record
+        Indices : Indices_t;
+    end record;
+
+    function Init(
+        TST_PKG_bus : Bus_t
+    ) return Bus_t;
+
+end package;
+
+package body TST_PKG is
+    function Init(
+        TST_PKG_bus : Bus_t
+    )
+    return Bus_t is
+        variable result : Bus_t(
+            Indices(TST_PKG_bus.Indices'range)(TST_PKG_bus.Indices'element'range)
+        );
+    begin
+        result.Indices := (others => (others => '0'));
+        return result;
+    end function Init;
+end package body;
+
+use work.tst_pkg.all;
+
+entity repro2 is
+end;
+
+architecture arch of repro2 is
+  constant c1 : bus_t := (indices => (1 to 4 => "01"));
+  constant c2 : bus_t := init (c1);
+begin
+end;
diff --git a/testsuite/gna/issue2071/testsuite.sh b/testsuite/gna/issue2071/testsuite.sh
new file mode 100755
index 000000000..b48031476
--- /dev/null
+++ b/testsuite/gna/issue2071/testsuite.sh
@@ -0,0 +1,14 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+export GHDL_STD_FLAGS=--std=08
+analyze repro.vhdl
+elab_simulate repro
+
+analyze tst.vhdl
+elab_simulate tst
+
+clean
+
+echo "Test successful"
diff --git a/testsuite/gna/issue2071/tst.vhdl b/testsuite/gna/issue2071/tst.vhdl
new file mode 100644
index 000000000..a8eb2c94d
--- /dev/null
+++ b/testsuite/gna/issue2071/tst.vhdl
@@ -0,0 +1,42 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+package TST_PKG is
+    type Indices_t is array (natural range <>) of std_logic_vector;
+
+    type Bus_t is record
+        Indices : Indices_t;
+    end record;
+
+    function Init(
+        TST_PKG_bus : Bus_t
+    ) return Bus_t;
+
+end package;
+
+package body TST_PKG is
+    function Init(
+        TST_PKG_bus : Bus_t
+    )
+    return Bus_t is
+        variable result : Bus_t(
+            Indices(TST_PKG_bus.Indices'range)(TST_PKG_bus.Indices'element'range)
+        );
+    begin
+        result.Indices := (others => (others => '0'));
+        return result;
+    end function Init;
+end package body;
+
+library ieee;
+use ieee.std_logic_1164.all;
+use work.tst_pkg.all;
+
+entity tst is
+end;
+
+architecture arch of tst is
+  constant c1 : bus_t := (indices => (1 to 4 => "01"));
+  constant c2 : bus_t := init (c1);
+begin
+end;