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-rw-r--r--testsuite/synth/issue1563/bug4.vhdl25
1 files changed, 25 insertions, 0 deletions
diff --git a/testsuite/synth/issue1563/bug4.vhdl b/testsuite/synth/issue1563/bug4.vhdl
new file mode 100644
index 000000000..2973e5798
--- /dev/null
+++ b/testsuite/synth/issue1563/bug4.vhdl
@@ -0,0 +1,25 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity bug4 is
+port (
+ clock : in std_logic;
+ output : out std_logic
+);
+end;
+
+architecture bug_arch OF bug4 is
+ signal t : std_logic := '1';
+begin
+ process (clock)
+ begin
+ if rising_edge(clock) then
+ t <= '1';
+ end if;
+ if rising_edge(clock) then
+ t <= '0';
+ end if;
+ end process;
+
+ output <= t;
+end bug_arch;