2 files changed, 30 insertions, 0 deletions
diff --git a/testsuite/synth/issue1237/mwe.vhdl b/testsuite/synth/issue1237/mwe.vhdl
new file mode 100644
index 000000000..0121b3a09
--- /dev/null
+++ b/testsuite/synth/issue1237/mwe.vhdl
@@ -0,0 +1,23 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity MWE is
+end MWE;
+
+architecture test of MWE is
+  constant P       : integer := 1;
+  signal   my_sig  : std_logic_vector(P downto 0);
+begin
+  block2: if P = 2 generate
+    my_sig(2) <= '1';
+  end generate;
+
+  block1: if P = 1 generate
+    my_sig(1) <= '1';
+  end generate;
+
+  -- even this block alone breaks during analysis
+  blockf: if false generate
+    my_sig(2) <= '1';
+  end generate;
+end architecture;
diff --git a/testsuite/synth/issue1237/testsuite.sh b/testsuite/synth/issue1237/testsuite.sh
new file mode 100755
index 000000000..fb89d4e19
--- /dev/null
+++ b/testsuite/synth/issue1237/testsuite.sh
@@ -0,0 +1,7 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+synth mwe.vhdl -e > syn_mwe.vhdl
+
+echo "Test successful"