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-rw-r--r--testsuite/synth/dff02/dff08b.vhdl26
1 files changed, 26 insertions, 0 deletions
diff --git a/testsuite/synth/dff02/dff08b.vhdl b/testsuite/synth/dff02/dff08b.vhdl
new file mode 100644
index 000000000..55b8f4dcb
--- /dev/null
+++ b/testsuite/synth/dff02/dff08b.vhdl
@@ -0,0 +1,26 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity dff08b is
+ port (q : out std_logic_vector(7 downto 0);
+ d : std_logic_vector(7 downto 0);
+ clk : std_logic;
+ en : std_logic;
+ rst : std_logic);
+end dff08b;
+
+architecture behav of dff08b is
+ signal p : std_logic_vector(7 downto 0) := x"aa";
+begin
+ process (clk, rst) is
+ begin
+ if en = '0' then
+ null;
+ elsif rst = '1' then
+ p <= x"00";
+ elsif rising_edge (clk) then
+ p <= d;
+ end if;
+ end process;
+ q <= p;
+end behav;