diff options
Diffstat (limited to 'pyGHDL/dom')
| -rw-r--r-- | pyGHDL/dom/Common.py | 9 | ||||
| -rw-r--r-- | pyGHDL/dom/DesignUnit.py | 44 | ||||
| -rw-r--r-- | pyGHDL/dom/Expression.py | 101 | ||||
| -rw-r--r-- | pyGHDL/dom/InterfaceItem.py | 27 | ||||
| -rw-r--r-- | pyGHDL/dom/Literal.py | 9 | ||||
| -rw-r--r-- | pyGHDL/dom/Misc.py | 56 | ||||
| -rw-r--r-- | pyGHDL/dom/Object.py | 25 | ||||
| -rw-r--r-- | pyGHDL/dom/Range.py | 10 | ||||
| -rw-r--r-- | pyGHDL/dom/Symbol.py | 12 | ||||
| -rw-r--r-- | pyGHDL/dom/_Translate.py | 64 | ||||
| -rw-r--r-- | pyGHDL/dom/_Utils.py | 15 | ||||
| -rw-r--r-- | pyGHDL/dom/formatting/prettyprint.py | 201 |
12 files changed, 377 insertions, 196 deletions
diff --git a/pyGHDL/dom/Common.py b/pyGHDL/dom/Common.py index 88d0cdc8c..984f06e86 100644 --- a/pyGHDL/dom/Common.py +++ b/pyGHDL/dom/Common.py @@ -37,8 +37,8 @@ """ from pydecor import export -from pyGHDL import GHDLBaseException -from pyGHDL.libghdl import LibGHDLException, errorout_memory +from pyGHDL import GHDLBaseException +from pyGHDL.libghdl import LibGHDLException, errorout_memory __all__ = [] @@ -61,5 +61,6 @@ class GHDLMixin: for i in range(errorCount): print(errorout_memory.Get_Error_Message(i + 1)) - raise DOMException("Error in libghdl.") \ - from LibGHDLException("libghdl: Internal error 2.") + raise DOMException("Error in libghdl.") from LibGHDLException( + "libghdl: Internal error 2." + ) diff --git a/pyGHDL/dom/DesignUnit.py b/pyGHDL/dom/DesignUnit.py index 9827cec24..dee86cab3 100644 --- a/pyGHDL/dom/DesignUnit.py +++ b/pyGHDL/dom/DesignUnit.py @@ -41,19 +41,24 @@ This module contains all DOM classes for VHDL's design units (:class:`context <E """ from pydecor import export -from pyVHDLModel.VHDLModel import Entity as VHDLModel_Entity -from pyVHDLModel.VHDLModel import Architecture as VHDLModel_Architecture -from pyVHDLModel.VHDLModel import Package as VHDLModel_Package -from pyVHDLModel.VHDLModel import PackageBody as VHDLModel_PackageBody -from pyVHDLModel.VHDLModel import Context as VHDLModel_Context +from pyVHDLModel.VHDLModel import Entity as VHDLModel_Entity +from pyVHDLModel.VHDLModel import Architecture as VHDLModel_Architecture +from pyVHDLModel.VHDLModel import Package as VHDLModel_Package +from pyVHDLModel.VHDLModel import PackageBody as VHDLModel_PackageBody +from pyVHDLModel.VHDLModel import Context as VHDLModel_Context from pyVHDLModel.VHDLModel import Configuration as VHDLModel_Configuration from pyGHDL.libghdl import utils from pyGHDL.libghdl.vhdl import nodes from pyGHDL.dom._Utils import NodeToName, GetIirKindOfNode -from pyGHDL.dom._Translate import GetExpressionFromNode, GetSubtypeIndicationFromNode, GetGenericsFromChainedNodes, GetPortsFromChainedNodes, \ - GetDeclaredItemsFromChainedNodes +from pyGHDL.dom._Translate import ( + GetExpressionFromNode, + GetSubtypeIndicationFromNode, + GetGenericsFromChainedNodes, + GetPortsFromChainedNodes, + GetDeclaredItemsFromChainedNodes, +) from pyGHDL.dom.Common import GHDLMixin, DOMException from pyGHDL.dom.Object import Constant, Signal @@ -62,19 +67,22 @@ __all__ = [] @export class Entity(VHDLModel_Entity, GHDLMixin): - @classmethod def parse(cls, libraryUnit): name = NodeToName(libraryUnit) entity = cls(name) - for generic in GetGenericsFromChainedNodes(nodes.Get_Generic_Chain(libraryUnit)): + for generic in GetGenericsFromChainedNodes( + nodes.Get_Generic_Chain(libraryUnit) + ): entity.GenericItems.append(generic) for port in GetPortsFromChainedNodes(nodes.Get_Port_Chain(libraryUnit)): entity.PortItems.append(port) - for item in GetDeclaredItemsFromChainedNodes(nodes.Get_Declaration_Chain(libraryUnit), "entity", name): + for item in GetDeclaredItemsFromChainedNodes( + nodes.Get_Declaration_Chain(libraryUnit), "entity", name + ): entity.DeclaredItems.append(item) return entity @@ -94,7 +102,9 @@ class Architecture(VHDLModel_Architecture, GHDLMixin): architecture = cls(name, entityName) - for item in GetDeclaredItemsFromChainedNodes(nodes.Get_Declaration_Chain(libraryUnit), "architecture", name): + for item in GetDeclaredItemsFromChainedNodes( + nodes.Get_Declaration_Chain(libraryUnit), "architecture", name + ): architecture.DeclaredItems.append(item) return architecture @@ -105,14 +115,15 @@ class Architecture(VHDLModel_Architecture, GHDLMixin): @export class Package(VHDLModel_Package, GHDLMixin): - @classmethod def parse(cls, libraryUnit): name = NodeToName(libraryUnit) package = cls(name) - for item in GetDeclaredItemsFromChainedNodes(nodes.Get_Declaration_Chain(libraryUnit), "package", name): + for item in GetDeclaredItemsFromChainedNodes( + nodes.Get_Declaration_Chain(libraryUnit), "package", name + ): package.DeclaredItems.append(item) return package @@ -120,14 +131,15 @@ class Package(VHDLModel_Package, GHDLMixin): @export class PackageBody(VHDLModel_PackageBody, GHDLMixin): - @classmethod def parse(cls, libraryUnit): name = NodeToName(libraryUnit) packageBody = cls(name) - for item in GetDeclaredItemsFromChainedNodes(nodes.Get_Declaration_Chain(libraryUnit), "package body", name): + for item in GetDeclaredItemsFromChainedNodes( + nodes.Get_Declaration_Chain(libraryUnit), "package body", name + ): packageBody.DeclaredItems.append(item) return packageBody @@ -135,7 +147,6 @@ class PackageBody(VHDLModel_PackageBody, GHDLMixin): @export class Context(VHDLModel_Context, GHDLMixin): - @classmethod def parse(cls, libraryUnit): name = NodeToName(libraryUnit) @@ -144,7 +155,6 @@ class Context(VHDLModel_Context, GHDLMixin): @export class Configuration(VHDLModel_Configuration, GHDLMixin): - @classmethod def parse(cls, libraryUnit): name = NodeToName(libraryUnit) diff --git a/pyGHDL/dom/Expression.py b/pyGHDL/dom/Expression.py index 7f32e7d54..754b73304 100644 --- a/pyGHDL/dom/Expression.py +++ b/pyGHDL/dom/Expression.py @@ -32,85 +32,94 @@ # ============================================================================ from pydecor import export -from pyVHDLModel.VHDLModel import \ - InverseExpression as VHDLModel_InverseExpression, \ - IdentityExpression as VHDLModel_IdentityExpression, \ - NegationExpression as VHDLModel_NegationExpression, \ - AbsoluteExpression as VHDLModel_AbsoluteExpression, \ - TypeConversion as VHDLModel_TypeConversion, \ - FunctionCall as VHDLModel_FunctionCall, \ - QualifiedExpression as VHDLModel_QualifiedExpression, \ - AdditionExpression as VHDLModel_AdditionExpression, \ - SubtractionExpression as VHDLModel_SubtractionExpression, \ - ConcatenationExpression as VHDLModel_ConcatenationExpression, \ - MultiplyExpression as VHDLModel_MultiplyExpression, \ - DivisionExpression as VHDLModel_DivisionExpression, \ - RemainderExpression as VHDLModel_RemainderExpression, \ - ModuloExpression as VHDLModel_ModuloExpression, \ - ExponentiationExpression as VHDLModel_ExponentiationExpression, \ - AndExpression as VHDLModel_AndExpression, \ - NandExpression as VHDLModel_NandExpression, \ - OrExpression as VHDLModel_OrExpression, \ - NorExpression as VHDLModel_NorExpression, \ - XorExpression as VHDLModel_XorExpression, \ - XnorExpression as VHDLModel_XnorExpression, \ - EqualExpression as VHDLModel_EqualExpression, \ - UnequalExpression as VHDLModel_UnequalExpression, \ - GreaterThanExpression as VHDLModel_GreaterThanExpression, \ - GreaterEqualExpression as VHDLModel_GreaterEqualExpression, \ - LessThanExpression as VHDLModel_LessThanExpression, \ - ShiftRightLogicExpression as VHDLModel_ShiftRightLogicExpression, \ - ShiftLeftLogicExpression as VHDLModel_ShiftLeftLogicExpression, \ - ShiftRightArithmeticExpression as VHDLModel_ShiftRightArithmeticExpression, \ - ShiftLeftArithmeticExpression as VHDLModel_ShiftLeftArithmeticExpression, \ - RotateRightExpression as VHDLModel_RotateRightExpression, \ - RotateLeftExpression as VHDLModel_RotateLeftExpression, \ - Expression +from pyVHDLModel.VHDLModel import ( + InverseExpression as VHDLModel_InverseExpression, + IdentityExpression as VHDLModel_IdentityExpression, + NegationExpression as VHDLModel_NegationExpression, + AbsoluteExpression as VHDLModel_AbsoluteExpression, + TypeConversion as VHDLModel_TypeConversion, + FunctionCall as VHDLModel_FunctionCall, + QualifiedExpression as VHDLModel_QualifiedExpression, + AdditionExpression as VHDLModel_AdditionExpression, + SubtractionExpression as VHDLModel_SubtractionExpression, + ConcatenationExpression as VHDLModel_ConcatenationExpression, + MultiplyExpression as VHDLModel_MultiplyExpression, + DivisionExpression as VHDLModel_DivisionExpression, + RemainderExpression as VHDLModel_RemainderExpression, + ModuloExpression as VHDLModel_ModuloExpression, + ExponentiationExpression as VHDLModel_ExponentiationExpression, + AndExpression as VHDLModel_AndExpression, + NandExpression as VHDLModel_NandExpression, + OrExpression as VHDLModel_OrExpression, + NorExpression as VHDLModel_NorExpression, + XorExpression as VHDLModel_XorExpression, + XnorExpression as VHDLModel_XnorExpression, + EqualExpression as VHDLModel_EqualExpression, + UnequalExpression as VHDLModel_UnequalExpression, + GreaterThanExpression as VHDLModel_GreaterThanExpression, + GreaterEqualExpression as VHDLModel_GreaterEqualExpression, + LessThanExpression as VHDLModel_LessThanExpression, + ShiftRightLogicExpression as VHDLModel_ShiftRightLogicExpression, + ShiftLeftLogicExpression as VHDLModel_ShiftLeftLogicExpression, + ShiftRightArithmeticExpression as VHDLModel_ShiftRightArithmeticExpression, + ShiftLeftArithmeticExpression as VHDLModel_ShiftLeftArithmeticExpression, + RotateRightExpression as VHDLModel_RotateRightExpression, + RotateLeftExpression as VHDLModel_RotateLeftExpression, + Expression, +) __all__ = [] + @export class InverseExpression(VHDLModel_InverseExpression): def __init__(self, operand: Expression): super().__init__() self._operand = operand + @export class IdentityExpression(VHDLModel_IdentityExpression): def __init__(self, operand: Expression): super().__init__() self._operand = operand + @export class NegationExpression(VHDLModel_NegationExpression): def __init__(self, operand: Expression): super().__init__() self._operand = operand + @export class AbsoluteExpression(VHDLModel_AbsoluteExpression): def __init__(self, operand: Expression): super().__init__() self._operand = operand + @export class TypeConversion(VHDLModel_TypeConversion): def __init__(self, operand: Expression): super().__init__() self._operand = operand + @export class FunctionCall(VHDLModel_FunctionCall): def __init__(self, operand: Expression): super().__init__() self._operand = operand + @export class QualifiedExpression(VHDLModel_QualifiedExpression): def __init__(self, operand: Expression): super().__init__() self._operand = operand + @export class AdditionExpression(VHDLModel_AdditionExpression): def __init__(self, left: Expression, right: Expression): @@ -118,6 +127,7 @@ class AdditionExpression(VHDLModel_AdditionExpression): self._leftOperand = left self._rightOperand = right + @export class SubtractionExpression(VHDLModel_SubtractionExpression): def __init__(self, left: Expression, right: Expression): @@ -125,6 +135,7 @@ class SubtractionExpression(VHDLModel_SubtractionExpression): self._leftOperand = left self._rightOperand = right + @export class ConcatenationExpression(VHDLModel_ConcatenationExpression): def __init__(self, left: Expression, right: Expression): @@ -132,6 +143,7 @@ class ConcatenationExpression(VHDLModel_ConcatenationExpression): self._leftOperand = left self._rightOperand = right + @export class MultiplyExpression(VHDLModel_MultiplyExpression): def __init__(self, left: Expression, right: Expression): @@ -139,6 +151,7 @@ class MultiplyExpression(VHDLModel_MultiplyExpression): self._leftOperand = left self._rightOperand = right + @export class DivisionExpression(VHDLModel_DivisionExpression): def __init__(self, left: Expression, right: Expression): @@ -146,6 +159,7 @@ class DivisionExpression(VHDLModel_DivisionExpression): self._leftOperand = left self._rightOperand = right + @export class RemainderExpression(VHDLModel_RemainderExpression): def __init__(self, left: Expression, right: Expression): @@ -153,6 +167,7 @@ class RemainderExpression(VHDLModel_RemainderExpression): self._leftOperand = left self._rightOperand = right + @export class ModuloExpression(VHDLModel_ModuloExpression): def __init__(self, left: Expression, right: Expression): @@ -160,6 +175,7 @@ class ModuloExpression(VHDLModel_ModuloExpression): self._leftOperand = left self._rightOperand = right + @export class ExponentiationExpression(VHDLModel_ExponentiationExpression): def __init__(self, left: Expression, right: Expression): @@ -167,6 +183,7 @@ class ExponentiationExpression(VHDLModel_ExponentiationExpression): self._leftOperand = left self._rightOperand = right + @export class AndExpression(VHDLModel_AndExpression): def __init__(self, left: Expression, right: Expression): @@ -174,6 +191,7 @@ class AndExpression(VHDLModel_AndExpression): self._leftOperand = left self._rightOperand = right + @export class NandExpression(VHDLModel_NandExpression): def __init__(self, left: Expression, right: Expression): @@ -181,6 +199,7 @@ class NandExpression(VHDLModel_NandExpression): self._leftOperand = left self._rightOperand = right + @export class OrExpression(VHDLModel_OrExpression): def __init__(self, left: Expression, right: Expression): @@ -188,6 +207,7 @@ class OrExpression(VHDLModel_OrExpression): self._leftOperand = left self._rightOperand = right + @export class NorExpression(VHDLModel_NorExpression): def __init__(self, left: Expression, right: Expression): @@ -195,6 +215,7 @@ class NorExpression(VHDLModel_NorExpression): self._leftOperand = left self._rightOperand = right + @export class XorExpression(VHDLModel_XorExpression): def __init__(self, left: Expression, right: Expression): @@ -202,6 +223,7 @@ class XorExpression(VHDLModel_XorExpression): self._leftOperand = left self._rightOperand = right + @export class XnorExpression(VHDLModel_XnorExpression): def __init__(self, left: Expression, right: Expression): @@ -209,6 +231,7 @@ class XnorExpression(VHDLModel_XnorExpression): self._leftOperand = left self._rightOperand = right + @export class EqualExpression(VHDLModel_EqualExpression): def __init__(self, left: Expression, right: Expression): @@ -216,6 +239,7 @@ class EqualExpression(VHDLModel_EqualExpression): self._leftOperand = left self._rightOperand = right + @export class UnequalExpression(VHDLModel_UnequalExpression): def __init__(self, left: Expression, right: Expression): @@ -223,6 +247,7 @@ class UnequalExpression(VHDLModel_UnequalExpression): self._leftOperand = left self._rightOperand = right + @export class GreaterThanExpression(VHDLModel_GreaterThanExpression): def __init__(self, left: Expression, right: Expression): @@ -230,6 +255,7 @@ class GreaterThanExpression(VHDLModel_GreaterThanExpression): self._leftOperand = left self._rightOperand = right + @export class GreaterEqualExpression(VHDLModel_GreaterEqualExpression): def __init__(self, left: Expression, right: Expression): @@ -237,6 +263,7 @@ class GreaterEqualExpression(VHDLModel_GreaterEqualExpression): self._leftOperand = left self._rightOperand = right + @export class LessThanExpression(VHDLModel_LessThanExpression): def __init__(self, left: Expression, right: Expression): @@ -244,6 +271,7 @@ class LessThanExpression(VHDLModel_LessThanExpression): self._leftOperand = left self._rightOperand = right + @export class ShiftRightLogicExpression(VHDLModel_ShiftRightLogicExpression): def __init__(self, left: Expression, right: Expression): @@ -251,6 +279,7 @@ class ShiftRightLogicExpression(VHDLModel_ShiftRightLogicExpression): self._leftOperand = left self._rightOperand = right + @export class ShiftLeftLogicExpression(VHDLModel_ShiftLeftLogicExpression): def __init__(self, left: Expression, right: Expression): @@ -258,6 +287,7 @@ class ShiftLeftLogicExpression(VHDLModel_ShiftLeftLogicExpression): self._leftOperand = left self._rightOperand = right + @export class ShiftRightArithmeticExpression(VHDLModel_ShiftRightArithmeticExpression): def __init__(self, left: Expression, right: Expression): @@ -265,6 +295,7 @@ class ShiftRightArithmeticExpression(VHDLModel_ShiftRightArithmeticExpression): self._leftOperand = left self._rightOperand = right + @export class ShiftLeftArithmeticExpression(VHDLModel_ShiftLeftArithmeticExpression): def __init__(self, left: Expression, right: Expression): @@ -272,6 +303,7 @@ class ShiftLeftArithmeticExpression(VHDLModel_ShiftLeftArithmeticExpression): self._leftOperand = left self._rightOperand = right + @export class RotateRightExpression(VHDLModel_RotateRightExpression): def __init__(self, left: Expression, right: Expression): @@ -279,6 +311,7 @@ class RotateRightExpression(VHDLModel_RotateRightExpression): self._leftOperand = left self._rightOperand = right + @export class RotateLeftExpression(VHDLModel_RotateLeftExpression): def __init__(self, left: Expression, right: Expression): diff --git a/pyGHDL/dom/InterfaceItem.py b/pyGHDL/dom/InterfaceItem.py index 89427e3b4..028adc690 100644 --- a/pyGHDL/dom/InterfaceItem.py +++ b/pyGHDL/dom/InterfaceItem.py @@ -32,14 +32,17 @@ # ============================================================================ from pydecor import export -from pyVHDLModel.VHDLModel import \ - GenericConstantInterfaceItem as VHDLModel_GenericConstantInterfaceItem, \ - PortSignalInterfaceItem as VHDLModel_PortSignalInterfaceItem, \ - Mode, SubTypeOrSymbol, Expression +from pyVHDLModel.VHDLModel import ( + GenericConstantInterfaceItem as VHDLModel_GenericConstantInterfaceItem, + PortSignalInterfaceItem as VHDLModel_PortSignalInterfaceItem, + Mode, + SubTypeOrSymbol, + Expression, +) -from pyGHDL.dom._Utils import NodeToName, GetModeOfNode +from pyGHDL.dom._Utils import NodeToName, GetModeOfNode from pyGHDL.dom._Translate import GetSubtypeIndicationFromNode -from pyGHDL.dom.Common import GHDLMixin +from pyGHDL.dom.Common import GHDLMixin __all__ = [] @@ -56,10 +59,11 @@ class GenericConstantInterfaceItem(VHDLModel_GenericConstantInterfaceItem, GHDLM return generic - def __init__(self, name:str, mode: Mode, subType: SubTypeOrSymbol): + def __init__(self, name: str, mode: Mode, subType: SubTypeOrSymbol): super().__init__(name=name, mode=mode) self._subType = subType + @export class PortSignalInterfaceItem(VHDLModel_PortSignalInterfaceItem, GHDLMixin): @classmethod @@ -72,8 +76,13 @@ class PortSignalInterfaceItem(VHDLModel_PortSignalInterfaceItem, GHDLMixin): return port - def __init__(self, name:str, mode: Mode, subType: SubTypeOrSymbol, defaultExpression: Expression = None): + def __init__( + self, + name: str, + mode: Mode, + subType: SubTypeOrSymbol, + defaultExpression: Expression = None, + ): super().__init__(name=name, mode=mode) self._subType = subType self._defaultExpression = defaultExpression - diff --git a/pyGHDL/dom/Literal.py b/pyGHDL/dom/Literal.py index 2ed1b5f65..562b188fd 100644 --- a/pyGHDL/dom/Literal.py +++ b/pyGHDL/dom/Literal.py @@ -32,10 +32,11 @@ # ============================================================================ from pydecor import export -from pyVHDLModel.VHDLModel import \ - IntegerLiteral as VHDLModel_IntegerLiteral, \ - FloatingPointLiteral as VHDLModel_FloatingPointLiteral, \ - CharacterLiteral as VHDLModel_CharacterLiteral +from pyVHDLModel.VHDLModel import ( + IntegerLiteral as VHDLModel_IntegerLiteral, + FloatingPointLiteral as VHDLModel_FloatingPointLiteral, + CharacterLiteral as VHDLModel_CharacterLiteral, +) __all__ = [] diff --git a/pyGHDL/dom/Misc.py b/pyGHDL/dom/Misc.py index 0f26119a2..837234a9a 100644 --- a/pyGHDL/dom/Misc.py +++ b/pyGHDL/dom/Misc.py @@ -36,22 +36,35 @@ Add a module documentation. """ from pathlib import Path -from typing import Any +from typing import Any import pyGHDL.libghdl.utils from pydecor import export from pyGHDL.dom._Utils import GetIirKindOfNode -from pyVHDLModel.VHDLModel import Design as VHDLModel_Design -from pyVHDLModel.VHDLModel import Library as VHDLModel_Library -from pyVHDLModel.VHDLModel import Document as VHDLModel_Document - -import pyGHDL.libghdl as libghdl -from pyGHDL.libghdl import name_table, files_map, errorout_memory, LibGHDLException, utils -from pyGHDL.libghdl.vhdl import nodes, sem_lib - -from pyGHDL.dom.Common import DOMException, GHDLMixin -from pyGHDL.dom.DesignUnit import Entity, Architecture, Package, PackageBody, Context, Configuration +from pyVHDLModel.VHDLModel import Design as VHDLModel_Design +from pyVHDLModel.VHDLModel import Library as VHDLModel_Library +from pyVHDLModel.VHDLModel import Document as VHDLModel_Document + +import pyGHDL.libghdl as libghdl +from pyGHDL.libghdl import ( + name_table, + files_map, + errorout_memory, + LibGHDLException, + utils, +) +from pyGHDL.libghdl.vhdl import nodes, sem_lib + +from pyGHDL.dom.Common import DOMException, GHDLMixin +from pyGHDL.dom.DesignUnit import ( + Entity, + Architecture, + Package, + PackageBody, + Context, + Configuration, +) __all__ = [] @@ -95,13 +108,15 @@ class Document(VHDLModel_Document, GHDLMixin): GHDLMixin.__init__(self) self.__ghdl_init() - if (dontParse == False): + if dontParse == False: self.parse() def __ghdl_init(self): # Read input file self.__ghdlFileID = name_table.Get_Identifier(str(self.Path)) - self.__ghdlSourceFileEntry = files_map.Read_Source_File(name_table.Null_Identifier, self.__ghdlFileID) + self.__ghdlSourceFileEntry = files_map.Read_Source_File( + name_table.Null_Identifier, self.__ghdlFileID + ) if self.__ghdlSourceFileEntry == files_map.No_Source_File_Entry: raise LibGHDLException("Cannot load file '{!s}'".format(self.Path)) @@ -119,32 +134,33 @@ class Document(VHDLModel_Document, GHDLMixin): libraryUnit = nodes.Get_Library_Unit(unit) nodeKind = GetIirKindOfNode(libraryUnit) - if (nodeKind == nodes.Iir_Kind.Entity_Declaration): + if nodeKind == nodes.Iir_Kind.Entity_Declaration: entity = Entity.parse(libraryUnit) self.Entities.append(entity) - elif (nodeKind == nodes.Iir_Kind.Architecture_Body): + elif nodeKind == nodes.Iir_Kind.Architecture_Body: architecture = Architecture.parse(libraryUnit) self.Architectures.append(architecture) - elif (nodeKind == nodes.Iir_Kind.Package_Declaration): + elif nodeKind == nodes.Iir_Kind.Package_Declaration: package = Package.parse(libraryUnit) self.Packages.append(package) - elif (nodeKind == nodes.Iir_Kind.Package_Body): + elif nodeKind == nodes.Iir_Kind.Package_Body: packageBody = PackageBody.parse(libraryUnit) self.PackageBodies.append(packageBody) - elif (nodeKind == nodes.Iir_Kind.Context_Declaration): + elif nodeKind == nodes.Iir_Kind.Context_Declaration: context = Context.parse(libraryUnit) self.Contexts.append(context) - elif (nodeKind == nodes.Iir_Kind.Configuration_Declaration): + elif nodeKind == nodes.Iir_Kind.Configuration_Declaration: configuration = Configuration.parse(libraryUnit) self.Configurations.append(configuration) else: raise DOMException( "Unknown design unit kind '{kindName}'({kind}).".format( - kindName=nodeKind.name, kind=nodeKind) + kindName=nodeKind.name, kind=nodeKind + ) ) diff --git a/pyGHDL/dom/Object.py b/pyGHDL/dom/Object.py index 924c28662..f719cbed5 100644 --- a/pyGHDL/dom/Object.py +++ b/pyGHDL/dom/Object.py @@ -32,18 +32,22 @@ # ============================================================================ from pydecor import export -from pyVHDLModel.VHDLModel import \ - Constant as VHDLModel_Constant, \ - Variable as VHDLModel_Variable, \ - Signal as VHDLModel_Signal, \ - Expression, SubTypeOrSymbol +from pyVHDLModel.VHDLModel import ( + Constant as VHDLModel_Constant, + Variable as VHDLModel_Variable, + Signal as VHDLModel_Signal, + Expression, + SubTypeOrSymbol, +) __all__ = [] @export class Constant(VHDLModel_Constant): - def __init__(self, name: str, subType: SubTypeOrSymbol, defaultExpression: Expression): + def __init__( + self, name: str, subType: SubTypeOrSymbol, defaultExpression: Expression + ): super().__init__(name) self._name = name @@ -53,7 +57,9 @@ class Constant(VHDLModel_Constant): @export class Variable(VHDLModel_Variable): - def __init__(self, name: str, subType: SubTypeOrSymbol, defaultExpression: Expression): + def __init__( + self, name: str, subType: SubTypeOrSymbol, defaultExpression: Expression + ): super().__init__(name) self._name = name @@ -63,10 +69,11 @@ class Variable(VHDLModel_Variable): @export class Signal(VHDLModel_Signal): - def __init__(self, name: str, subType: SubTypeOrSymbol, defaultExpression: Expression): + def __init__( + self, name: str, subType: SubTypeOrSymbol, defaultExpression: Expression + ): super().__init__(name) self._name = name self._subType = subType self._defaultExpression = defaultExpression - diff --git a/pyGHDL/dom/Range.py b/pyGHDL/dom/Range.py index 45675cd19..1a5ac518c 100644 --- a/pyGHDL/dom/Range.py +++ b/pyGHDL/dom/Range.py @@ -32,10 +32,12 @@ # ============================================================================ from pydecor import export -from pyVHDLModel.VHDLModel import \ - Range as VHDLModel_Range, \ - RangeExpression as VHDLModel_RangeExpression, \ - Direction, Expression +from pyVHDLModel.VHDLModel import ( + Range as VHDLModel_Range, + RangeExpression as VHDLModel_RangeExpression, + Direction, + Expression, +) __all__ = [] diff --git a/pyGHDL/dom/Symbol.py b/pyGHDL/dom/Symbol.py index 9b765872d..09774a634 100644 --- a/pyGHDL/dom/Symbol.py +++ b/pyGHDL/dom/Symbol.py @@ -34,11 +34,12 @@ from pydecor import export from typing import List -from pyVHDLModel.VHDLModel import \ - SimpleSubTypeSymbol as VHDLModel_SimpleSubTypeSymbol, \ - ConstrainedSubTypeSymbol as VHDLModel_ConstrainedSubTypeSymbol, \ - SimpleObjectSymbol as VHDLModel_SimpleObjectSymbol, \ - Constraint +from pyVHDLModel.VHDLModel import ( + SimpleSubTypeSymbol as VHDLModel_SimpleSubTypeSymbol, + ConstrainedSubTypeSymbol as VHDLModel_ConstrainedSubTypeSymbol, + SimpleObjectSymbol as VHDLModel_SimpleObjectSymbol, + Constraint, +) __all__ = [] @@ -54,6 +55,7 @@ class ConstrainedSubTypeSymbol(VHDLModel_ConstrainedSubTypeSymbol): def __init__(self, subTypeName: str, constraints: List[Constraint] = None): super().__init__(subTypeName=subTypeName, constraints=constraints) + @export class SimpleObjectSymbol(VHDLModel_SimpleObjectSymbol): def __init__(self, symbolName: str): diff --git a/pyGHDL/dom/_Translate.py b/pyGHDL/dom/_Translate.py index e93b20b07..9435010ab 100644 --- a/pyGHDL/dom/_Translate.py +++ b/pyGHDL/dom/_Translate.py @@ -5,14 +5,25 @@ from pydecor import export from pyVHDLModel.VHDLModel import Constraint, Direction, Expression, SubTypeOrSymbol from pyGHDL.libghdl import utils, name_table -from pyGHDL.libghdl.utils import flist_iter -from pyGHDL.libghdl.vhdl import nodes -from pyGHDL.dom._Utils import NodeToName, GetIirKindOfNode -from pyGHDL.dom.Common import DOMException -from pyGHDL.dom.Range import Range, RangeExpression -from pyGHDL.dom.Symbol import SimpleObjectSymbol, SimpleSubTypeSymbol, ConstrainedSubTypeSymbol +from pyGHDL.libghdl.utils import flist_iter +from pyGHDL.libghdl.vhdl import nodes +from pyGHDL.dom._Utils import NodeToName, GetIirKindOfNode +from pyGHDL.dom.Common import DOMException +from pyGHDL.dom.Range import Range, RangeExpression +from pyGHDL.dom.Symbol import ( + SimpleObjectSymbol, + SimpleSubTypeSymbol, + ConstrainedSubTypeSymbol, +) from pyGHDL.dom.Literal import IntegerLiteral, CharacterLiteral, FloatingPointLiteral -from pyGHDL.dom.Expression import SubtractionExpression, AdditionExpression, MultiplyExpression, DivisionExpression, InverseExpression, ExponentiationExpression +from pyGHDL.dom.Expression import ( + SubtractionExpression, + AdditionExpression, + MultiplyExpression, + DivisionExpression, + InverseExpression, + ExponentiationExpression, +) __all__ = [] @@ -22,29 +33,32 @@ def GetSubtypeIndicationFromNode(node, entity: str, name: str) -> SubTypeOrSymbo subTypeIndication = nodes.Get_Subtype_Indication(node) subTypeKind = GetIirKindOfNode(subTypeIndication) - if (subTypeKind == nodes.Iir_Kind.Simple_Name): + if subTypeKind == nodes.Iir_Kind.Simple_Name: subTypeName = NodeToName(subTypeIndication) subType = SimpleSubTypeSymbol(subTypeName) - elif (subTypeKind == nodes.Iir_Kind.Array_Subtype_Definition): + elif subTypeKind == nodes.Iir_Kind.Array_Subtype_Definition: typeMark = nodes.Get_Subtype_Type_Mark(subTypeIndication) typeMarkName = NodeToName(typeMark) constraints = GetArrayConstraintsFromSubtypeIndication(subTypeIndication) subType = ConstrainedSubTypeSymbol(typeMarkName, constraints) - elif (subTypeKind == nodes.Iir_Kind.Subtype_Definition): + elif subTypeKind == nodes.Iir_Kind.Subtype_Definition: raise DOMException( "Unknown handling of subtype kind '{kind}' of subtype indication '{indication}' while parsing {entity} '{name}'.".format( - kind=subTypeKind, indication=subTypeIndication, entity=entity, name=name) + kind=subTypeKind, indication=subTypeIndication, entity=entity, name=name + ) ) else: raise DOMException( "Unknown subtype kind '{kind}' of subtype indication '{indication}' while parsing {entity} '{name}'.".format( - kind=subTypeKind, indication=subTypeIndication, entity=entity, name=name) + kind=subTypeKind, indication=subTypeIndication, entity=entity, name=name + ) ) return subType + @export def GetArrayConstraintsFromSubtypeIndication(subTypeIndication) -> List[Constraint]: constraints = [] @@ -58,7 +72,7 @@ def GetArrayConstraintsFromSubtypeIndication(subTypeIndication) -> List[Constrai r = Range( GetExpressionFromNode(leftBound), GetExpressionFromNode(rightBound), - Direction.DownTo if direction else Direction.To + Direction.DownTo if direction else Direction.To, ) constraints.append(RangeExpression(r)) elif constraintKind == nodes.Iir_Kind.Attribute_Name: @@ -68,7 +82,10 @@ def GetArrayConstraintsFromSubtypeIndication(subTypeIndication) -> List[Constrai else: raise DOMException( "Unknown constraint kind '{kind}' for constraint '{constraint}' in subtype indication '{indication}'.".format( - kind=constraintKind, constraint=constraint, indication=subTypeIndication) + kind=constraintKind, + constraint=constraint, + indication=subTypeIndication, + ) ) return constraints @@ -117,9 +134,11 @@ def GetExpressionFromNode(node) -> Expression: else: raise DOMException( "Unknown expression kind '{kindName}'({kind}) in expression '{expr}'.".format( - kind=kind, kindName=kind.name, expr=node) + kind=kind, kindName=kind.name, expr=node + ) ) + # FIXME: rewrite to generator @export def GetGenericsFromChainedNodes(nodeChain): @@ -135,11 +154,13 @@ def GetGenericsFromChainedNodes(nodeChain): else: raise DOMException( "Unknown generic kind '{kindName}'({kind}) in generic '{generic}'.".format( - kind=kind, kindName=kind.name, generic=generic) + kind=kind, kindName=kind.name, generic=generic + ) ) return result + # FIXME: rewrite to generator @export def GetPortsFromChainedNodes(nodeChain): @@ -155,11 +176,13 @@ def GetPortsFromChainedNodes(nodeChain): else: raise DOMException( "Unknown port kind '{kindName}'({kind}) in port '{port}'.".format( - kind=kind, kindName=kind.name, port=port) + kind=kind, kindName=kind.name, port=port + ) ) return result + def GetDeclaredItemsFromChainedNodes(nodeChain, entity: str, name: str): result = [] for item in utils.chain_iter(nodeChain): @@ -168,7 +191,9 @@ def GetDeclaredItemsFromChainedNodes(nodeChain, entity: str, name: str): from pyGHDL.dom.Object import Constant constantName = NodeToName(item) - subTypeIndication = GetSubtypeIndicationFromNode(item, "constant", constantName) + subTypeIndication = GetSubtypeIndicationFromNode( + item, "constant", constantName + ) defaultExpression = GetExpressionFromNode(nodes.Get_Default_Value(item)) constant = Constant(constantName, subTypeIndication, defaultExpression) @@ -202,7 +227,8 @@ def GetDeclaredItemsFromChainedNodes(nodeChain, entity: str, name: str): else: raise DOMException( "Unknown declared item kind '{kindName}'({kind}) in {entity} '{name}'.".format( - kind=kind, kindName=kind.name, entity=entity, name=name) + kind=kind, kindName=kind.name, entity=entity, name=name + ) ) return result diff --git a/pyGHDL/dom/_Utils.py b/pyGHDL/dom/_Utils.py index f0c838517..b74bdfa96 100644 --- a/pyGHDL/dom/_Utils.py +++ b/pyGHDL/dom/_Utils.py @@ -1,21 +1,22 @@ from pydecor import export -from pyVHDLModel.VHDLModel import Mode +from pyVHDLModel.VHDLModel import Mode -from pyGHDL.libghdl import LibGHDLException, name_table +from pyGHDL.libghdl import LibGHDLException, name_table from pyGHDL.libghdl.vhdl import nodes __all__ = [] __MODE_TRANSLATION = { - nodes.Iir_Mode.In_Mode: Mode.In, - nodes.Iir_Mode.Out_Mode: Mode.Out, - nodes.Iir_Mode.Inout_Mode: Mode.InOut, - nodes.Iir_Mode.Buffer_Mode: Mode.Buffer, - nodes.Iir_Mode.Linkage_Mode: Mode.Linkage + nodes.Iir_Mode.In_Mode: Mode.In, + nodes.Iir_Mode.Out_Mode: Mode.Out, + nodes.Iir_Mode.Inout_Mode: Mode.InOut, + nodes.Iir_Mode.Buffer_Mode: Mode.Buffer, + nodes.Iir_Mode.Linkage_Mode: Mode.Linkage, } + @export def GetIirKindOfNode(node) -> nodes.Iir_Kind: kind: int = nodes.Get_Kind(node) diff --git a/pyGHDL/dom/formatting/prettyprint.py b/pyGHDL/dom/formatting/prettyprint.py index a64f2a4f5..387706cac 100644 --- a/pyGHDL/dom/formatting/prettyprint.py +++ b/pyGHDL/dom/formatting/prettyprint.py @@ -3,53 +3,83 @@ from typing import List, Union from pydecor import export from pyGHDL.dom.Object import Constant, Signal -from pyVHDLModel.VHDLModel import GenericInterfaceItem, Expression, Direction, Mode, NamedEntity, PortInterfaceItem, BinaryExpression, IdentityExpression, \ - UnaryExpression +from pyVHDLModel.VHDLModel import ( + GenericInterfaceItem, + Expression, + Direction, + Mode, + NamedEntity, + PortInterfaceItem, + BinaryExpression, + IdentityExpression, + UnaryExpression, +) from pyGHDL import GHDLBaseException from pyGHDL.dom.Misc import Document -from pyGHDL.dom.DesignUnit import Entity, Architecture, Package, PackageBody, Configuration, Context -from pyGHDL.dom.InterfaceItem import GenericConstantInterfaceItem, PortSignalInterfaceItem -from pyGHDL.dom.Symbol import SimpleSubTypeSymbol, ConstrainedSubTypeSymbol, SimpleObjectSymbol +from pyGHDL.dom.DesignUnit import ( + Entity, + Architecture, + Package, + PackageBody, + Configuration, + Context, +) +from pyGHDL.dom.InterfaceItem import ( + GenericConstantInterfaceItem, + PortSignalInterfaceItem, +) +from pyGHDL.dom.Symbol import ( + SimpleSubTypeSymbol, + ConstrainedSubTypeSymbol, + SimpleObjectSymbol, +) from pyGHDL.dom.Literal import IntegerLiteral, CharacterLiteral, FloatingPointLiteral -from pyGHDL.dom.Expression import SubtractionExpression, AdditionExpression, MultiplyExpression, DivisionExpression, InverseExpression, AbsoluteExpression, \ - NegationExpression, ExponentiationExpression +from pyGHDL.dom.Expression import ( + SubtractionExpression, + AdditionExpression, + MultiplyExpression, + DivisionExpression, + InverseExpression, + AbsoluteExpression, + NegationExpression, + ExponentiationExpression, +) StringBuffer = List[str] -DirectionTranslation = { - Direction.To: "to", - Direction.DownTo: "downto" -} +DirectionTranslation = {Direction.To: "to", Direction.DownTo: "downto"} ModeTranslation = { - Mode.In: "in", - Mode.Out: "out", - Mode.InOut: "inout", - Mode.Buffer: "buffer", - Mode.Linkage: "linkage" + Mode.In: "in", + Mode.Out: "out", + Mode.InOut: "inout", + Mode.Buffer: "buffer", + Mode.Linkage: "linkage", } UnaryExpressionTranslation = { - IdentityExpression: " +", - NegationExpression: " -", - InverseExpression: "not ", - AbsoluteExpression: "abs ", + IdentityExpression: " +", + NegationExpression: " -", + InverseExpression: "not ", + AbsoluteExpression: "abs ", } BinaryExpressionTranslation = { - AdditionExpression: " + ", - SubtractionExpression: " - ", - MultiplyExpression: " * ", - DivisionExpression: " / ", - ExponentiationExpression: "**" + AdditionExpression: " + ", + SubtractionExpression: " - ", + MultiplyExpression: " * ", + DivisionExpression: " / ", + ExponentiationExpression: "**", } + @export class PrettyPrintException(GHDLBaseException): pass + @export class PrettyPrint: # _buffer: StringBuffer @@ -60,30 +90,32 @@ class PrettyPrint: def formatDocument(self, document: Document, level: int = 0) -> StringBuffer: buffer = [] prefix = " " * level - buffer.append("{prefix}Document '{doc!s}':".format(doc=document.Path, prefix=prefix)) + buffer.append( + "{prefix}Document '{doc!s}':".format(doc=document.Path, prefix=prefix) + ) buffer.append("{prefix} Entities:".format(prefix=prefix)) for entity in document.Entities: - for line in self.formatEntity(entity, level+1): + for line in self.formatEntity(entity, level + 1): buffer.append(line) buffer.append("{prefix} Architectures:".format(prefix=prefix)) for architecture in document.Architectures: - for line in self.formatArchitecture(architecture, level+1): + for line in self.formatArchitecture(architecture, level + 1): buffer.append(line) buffer.append("{prefix} Packages:".format(prefix=prefix)) for package in document.Packages: - for line in self.formatPackage(package, level+1): + for line in self.formatPackage(package, level + 1): buffer.append(line) buffer.append("{prefix} PackageBodies:".format(prefix=prefix)) for packageBodies in document.PackageBodies: - for line in self.formatPackageBody(packageBodies, level+1): + for line in self.formatPackageBody(packageBodies, level + 1): buffer.append(line) buffer.append("{prefix} Configurations:".format(prefix=prefix)) for configuration in document.Configurations: - for line in self.formatConfiguration(configuration, level+1): + for line in self.formatConfiguration(configuration, level + 1): buffer.append(line) buffer.append("{prefix} Contexts:".format(prefix=prefix)) for context in document.Contexts: - for line in self.formatContext(context, level+1): + for line in self.formatContext(context, level + 1): buffer.append(line) return buffer @@ -107,7 +139,9 @@ class PrettyPrint: return buffer - def formatArchitecture(self, architecture: Architecture, level: int = 0) -> StringBuffer: + def formatArchitecture( + self, architecture: Architecture, level: int = 0 + ) -> StringBuffer: buffer = [] prefix = " " * level buffer.append("{prefix}- {name}".format(name=architecture.Name, prefix=prefix)) @@ -129,7 +163,9 @@ class PrettyPrint: return buffer - def formatPackageBody(self, packageBody: PackageBody, level: int = 0) -> StringBuffer: + def formatPackageBody( + self, packageBody: PackageBody, level: int = 0 + ) -> StringBuffer: buffer = [] prefix = " " * level buffer.append("{prefix}- {name}".format(name=packageBody.Name, prefix=prefix)) @@ -140,7 +176,9 @@ class PrettyPrint: return buffer - def formatConfiguration(self, configuration: Configuration, level: int = 0) -> StringBuffer: + def formatConfiguration( + self, configuration: Configuration, level: int = 0 + ) -> StringBuffer: buffer = [] prefix = " " * level buffer.append("{prefix}- {name}".format(name=configuration.Name, prefix=prefix)) @@ -154,19 +192,29 @@ class PrettyPrint: return buffer - def formatGeneric(self, generic: Union[NamedEntity, GenericInterfaceItem], level: int = 0) -> StringBuffer: + def formatGeneric( + self, generic: Union[NamedEntity, GenericInterfaceItem], level: int = 0 + ) -> StringBuffer: if isinstance(generic, GenericConstantInterfaceItem): return self.formatGenericConstant(generic, level) else: - raise PrettyPrintException("Unhandled generic kind for generic '{name}'.".format(name=generic.Name)) + raise PrettyPrintException( + "Unhandled generic kind for generic '{name}'.".format(name=generic.Name) + ) - def formatPort(self, port: Union[NamedEntity, PortInterfaceItem], level: int = 0) -> StringBuffer: + def formatPort( + self, port: Union[NamedEntity, PortInterfaceItem], level: int = 0 + ) -> StringBuffer: if isinstance(port, PortSignalInterfaceItem): return self.formatPortSignal(port, level) else: - raise PrettyPrintException("Unhandled port kind for port '{name}'.".format(name=port.Name)) + raise PrettyPrintException( + "Unhandled port kind for port '{name}'.".format(name=port.Name) + ) - def formatGenericConstant(self, generic: GenericConstantInterfaceItem, level: int = 0) -> StringBuffer: + def formatGenericConstant( + self, generic: GenericConstantInterfaceItem, level: int = 0 + ) -> StringBuffer: buffer = [] prefix = " " * level subType = generic.SubType @@ -176,7 +224,7 @@ class PrettyPrint: prefix=prefix, name=generic.Name, mode=ModeTranslation[generic.Mode], - type=subType.SymbolName + type=subType.SymbolName, ) ) elif isinstance(subType, ConstrainedSubTypeSymbol): @@ -187,19 +235,31 @@ class PrettyPrint: mode=ModeTranslation[generic.Mode], type=subType.SymbolName, constraints=", ".join( - ["{left} {dir} {right}".format( - left=self.formatExpression(constraint.Range.LeftBound), - right=self.formatExpression(constraint.Range.RightBound), - dir=DirectionTranslation[constraint.Range.Direction]) - for constraint in subType.Constraints]) + [ + "{left} {dir} {right}".format( + left=self.formatExpression(constraint.Range.LeftBound), + right=self.formatExpression( + constraint.Range.RightBound + ), + dir=DirectionTranslation[constraint.Range.Direction], + ) + for constraint in subType.Constraints + ] + ), ) ) else: - raise PrettyPrintException("Unhandled constraint kind for generic '{name}'.".format(name=generic.Name)) + raise PrettyPrintException( + "Unhandled constraint kind for generic '{name}'.".format( + name=generic.Name + ) + ) return buffer - def formatPortSignal(self, port: PortSignalInterfaceItem, level: int = 0) -> StringBuffer: + def formatPortSignal( + self, port: PortSignalInterfaceItem, level: int = 0 + ) -> StringBuffer: buffer = [] prefix = " " * level @@ -208,7 +268,9 @@ class PrettyPrint: prefix=prefix, name=port.Name, mode=ModeTranslation[port.Mode], - subtypeindication=self.formatSubtypeIndication(port.SubType, "port", port.Name) + subtypeindication=self.formatSubtypeIndication( + port.SubType, "port", port.Name + ), ) ) @@ -223,8 +285,10 @@ class PrettyPrint: "{prefix}- constant {name} : {subtype} := {expr}".format( prefix=prefix, name=item.Name, - subtype=self.formatSubtypeIndication(item.SubType, "constant", item.Name), - expr=self.formatExpression(item.DefaultExpression) + subtype=self.formatSubtypeIndication( + item.SubType, "constant", item.Name + ), + expr=self.formatExpression(item.DefaultExpression), ) ) elif isinstance(item, Signal): @@ -232,10 +296,14 @@ class PrettyPrint: "{prefix}- signal {name} : {subtype}{initValue}".format( prefix=prefix, name=item.Name, - subtype=self.formatSubtypeIndication(item.SubType, "signal", item.Name), + subtype=self.formatSubtypeIndication( + item.SubType, "signal", item.Name + ), initValue=" := {expr}".format( expr=self.formatExpression(item.DefaultExpression) - ) if item.DefaultExpression is not None else "" + ) + if item.DefaultExpression is not None + else "", ) ) else: @@ -248,19 +316,25 @@ class PrettyPrint: return "{type}".format(type=subTypeIndication.SymbolName) elif isinstance(subTypeIndication, ConstrainedSubTypeSymbol): constraints = ", ".join( - ["{left} {dir} {right}".format( - left=self.formatExpression(constraint.Range.LeftBound), - right=self.formatExpression(constraint.Range.RightBound), - dir=DirectionTranslation[constraint.Range.Direction] - ) for constraint in subTypeIndication.Constraints] + [ + "{left} {dir} {right}".format( + left=self.formatExpression(constraint.Range.LeftBound), + right=self.formatExpression(constraint.Range.RightBound), + dir=DirectionTranslation[constraint.Range.Direction], + ) + for constraint in subTypeIndication.Constraints + ] ) return "{type}({constraints})".format( - type=subTypeIndication.SymbolName, - constraints=constraints + type=subTypeIndication.SymbolName, constraints=constraints ) else: - raise PrettyPrintException("Unhandled constraint kind for {entity} '{name}'.".format(entity=entity, name=name)) + raise PrettyPrintException( + "Unhandled constraint kind for {entity} '{name}'.".format( + entity=entity, name=name + ) + ) def formatExpression(self, expression: Expression) -> str: if isinstance(expression, SimpleObjectSymbol): @@ -278,8 +352,7 @@ class PrettyPrint: raise PrettyPrintException("Unhandled operator for unary expression.") return "{operator}{operand}".format( - operand=self.formatExpression(expression.Operand), - operator=operator + operand=self.formatExpression(expression.Operand), operator=operator ) elif isinstance(expression, BinaryExpression): try: @@ -290,7 +363,7 @@ class PrettyPrint: return "{left}{operator}{right}".format( left=self.formatExpression(expression.LeftOperand), right=self.formatExpression(expression.RightOperand), - operator=operator + operator=operator, ) else: raise PrettyPrintException("Unhandled expression kind.") |