diff options
Diffstat (limited to 'pyGHDL/dom/Expression.py')
| -rw-r--r-- | pyGHDL/dom/Expression.py | 101 |
1 files changed, 67 insertions, 34 deletions
diff --git a/pyGHDL/dom/Expression.py b/pyGHDL/dom/Expression.py index 7f32e7d54..754b73304 100644 --- a/pyGHDL/dom/Expression.py +++ b/pyGHDL/dom/Expression.py @@ -32,85 +32,94 @@ # ============================================================================ from pydecor import export -from pyVHDLModel.VHDLModel import \ - InverseExpression as VHDLModel_InverseExpression, \ - IdentityExpression as VHDLModel_IdentityExpression, \ - NegationExpression as VHDLModel_NegationExpression, \ - AbsoluteExpression as VHDLModel_AbsoluteExpression, \ - TypeConversion as VHDLModel_TypeConversion, \ - FunctionCall as VHDLModel_FunctionCall, \ - QualifiedExpression as VHDLModel_QualifiedExpression, \ - AdditionExpression as VHDLModel_AdditionExpression, \ - SubtractionExpression as VHDLModel_SubtractionExpression, \ - ConcatenationExpression as VHDLModel_ConcatenationExpression, \ - MultiplyExpression as VHDLModel_MultiplyExpression, \ - DivisionExpression as VHDLModel_DivisionExpression, \ - RemainderExpression as VHDLModel_RemainderExpression, \ - ModuloExpression as VHDLModel_ModuloExpression, \ - ExponentiationExpression as VHDLModel_ExponentiationExpression, \ - AndExpression as VHDLModel_AndExpression, \ - NandExpression as VHDLModel_NandExpression, \ - OrExpression as VHDLModel_OrExpression, \ - NorExpression as VHDLModel_NorExpression, \ - XorExpression as VHDLModel_XorExpression, \ - XnorExpression as VHDLModel_XnorExpression, \ - EqualExpression as VHDLModel_EqualExpression, \ - UnequalExpression as VHDLModel_UnequalExpression, \ - GreaterThanExpression as VHDLModel_GreaterThanExpression, \ - GreaterEqualExpression as VHDLModel_GreaterEqualExpression, \ - LessThanExpression as VHDLModel_LessThanExpression, \ - ShiftRightLogicExpression as VHDLModel_ShiftRightLogicExpression, \ - ShiftLeftLogicExpression as VHDLModel_ShiftLeftLogicExpression, \ - ShiftRightArithmeticExpression as VHDLModel_ShiftRightArithmeticExpression, \ - ShiftLeftArithmeticExpression as VHDLModel_ShiftLeftArithmeticExpression, \ - RotateRightExpression as VHDLModel_RotateRightExpression, \ - RotateLeftExpression as VHDLModel_RotateLeftExpression, \ - Expression +from pyVHDLModel.VHDLModel import ( + InverseExpression as VHDLModel_InverseExpression, + IdentityExpression as VHDLModel_IdentityExpression, + NegationExpression as VHDLModel_NegationExpression, + AbsoluteExpression as VHDLModel_AbsoluteExpression, + TypeConversion as VHDLModel_TypeConversion, + FunctionCall as VHDLModel_FunctionCall, + QualifiedExpression as VHDLModel_QualifiedExpression, + AdditionExpression as VHDLModel_AdditionExpression, + SubtractionExpression as VHDLModel_SubtractionExpression, + ConcatenationExpression as VHDLModel_ConcatenationExpression, + MultiplyExpression as VHDLModel_MultiplyExpression, + DivisionExpression as VHDLModel_DivisionExpression, + RemainderExpression as VHDLModel_RemainderExpression, + ModuloExpression as VHDLModel_ModuloExpression, + ExponentiationExpression as VHDLModel_ExponentiationExpression, + AndExpression as VHDLModel_AndExpression, + NandExpression as VHDLModel_NandExpression, + OrExpression as VHDLModel_OrExpression, + NorExpression as VHDLModel_NorExpression, + XorExpression as VHDLModel_XorExpression, + XnorExpression as VHDLModel_XnorExpression, + EqualExpression as VHDLModel_EqualExpression, + UnequalExpression as VHDLModel_UnequalExpression, + GreaterThanExpression as VHDLModel_GreaterThanExpression, + GreaterEqualExpression as VHDLModel_GreaterEqualExpression, + LessThanExpression as VHDLModel_LessThanExpression, + ShiftRightLogicExpression as VHDLModel_ShiftRightLogicExpression, + ShiftLeftLogicExpression as VHDLModel_ShiftLeftLogicExpression, + ShiftRightArithmeticExpression as VHDLModel_ShiftRightArithmeticExpression, + ShiftLeftArithmeticExpression as VHDLModel_ShiftLeftArithmeticExpression, + RotateRightExpression as VHDLModel_RotateRightExpression, + RotateLeftExpression as VHDLModel_RotateLeftExpression, + Expression, +) __all__ = [] + @export class InverseExpression(VHDLModel_InverseExpression): def __init__(self, operand: Expression): super().__init__() self._operand = operand + @export class IdentityExpression(VHDLModel_IdentityExpression): def __init__(self, operand: Expression): super().__init__() self._operand = operand + @export class NegationExpression(VHDLModel_NegationExpression): def __init__(self, operand: Expression): super().__init__() self._operand = operand + @export class AbsoluteExpression(VHDLModel_AbsoluteExpression): def __init__(self, operand: Expression): super().__init__() self._operand = operand + @export class TypeConversion(VHDLModel_TypeConversion): def __init__(self, operand: Expression): super().__init__() self._operand = operand + @export class FunctionCall(VHDLModel_FunctionCall): def __init__(self, operand: Expression): super().__init__() self._operand = operand + @export class QualifiedExpression(VHDLModel_QualifiedExpression): def __init__(self, operand: Expression): super().__init__() self._operand = operand + @export class AdditionExpression(VHDLModel_AdditionExpression): def __init__(self, left: Expression, right: Expression): @@ -118,6 +127,7 @@ class AdditionExpression(VHDLModel_AdditionExpression): self._leftOperand = left self._rightOperand = right + @export class SubtractionExpression(VHDLModel_SubtractionExpression): def __init__(self, left: Expression, right: Expression): @@ -125,6 +135,7 @@ class SubtractionExpression(VHDLModel_SubtractionExpression): self._leftOperand = left self._rightOperand = right + @export class ConcatenationExpression(VHDLModel_ConcatenationExpression): def __init__(self, left: Expression, right: Expression): @@ -132,6 +143,7 @@ class ConcatenationExpression(VHDLModel_ConcatenationExpression): self._leftOperand = left self._rightOperand = right + @export class MultiplyExpression(VHDLModel_MultiplyExpression): def __init__(self, left: Expression, right: Expression): @@ -139,6 +151,7 @@ class MultiplyExpression(VHDLModel_MultiplyExpression): self._leftOperand = left self._rightOperand = right + @export class DivisionExpression(VHDLModel_DivisionExpression): def __init__(self, left: Expression, right: Expression): @@ -146,6 +159,7 @@ class DivisionExpression(VHDLModel_DivisionExpression): self._leftOperand = left self._rightOperand = right + @export class RemainderExpression(VHDLModel_RemainderExpression): def __init__(self, left: Expression, right: Expression): @@ -153,6 +167,7 @@ class RemainderExpression(VHDLModel_RemainderExpression): self._leftOperand = left self._rightOperand = right + @export class ModuloExpression(VHDLModel_ModuloExpression): def __init__(self, left: Expression, right: Expression): @@ -160,6 +175,7 @@ class ModuloExpression(VHDLModel_ModuloExpression): self._leftOperand = left self._rightOperand = right + @export class ExponentiationExpression(VHDLModel_ExponentiationExpression): def __init__(self, left: Expression, right: Expression): @@ -167,6 +183,7 @@ class ExponentiationExpression(VHDLModel_ExponentiationExpression): self._leftOperand = left self._rightOperand = right + @export class AndExpression(VHDLModel_AndExpression): def __init__(self, left: Expression, right: Expression): @@ -174,6 +191,7 @@ class AndExpression(VHDLModel_AndExpression): self._leftOperand = left self._rightOperand = right + @export class NandExpression(VHDLModel_NandExpression): def __init__(self, left: Expression, right: Expression): @@ -181,6 +199,7 @@ class NandExpression(VHDLModel_NandExpression): self._leftOperand = left self._rightOperand = right + @export class OrExpression(VHDLModel_OrExpression): def __init__(self, left: Expression, right: Expression): @@ -188,6 +207,7 @@ class OrExpression(VHDLModel_OrExpression): self._leftOperand = left self._rightOperand = right + @export class NorExpression(VHDLModel_NorExpression): def __init__(self, left: Expression, right: Expression): @@ -195,6 +215,7 @@ class NorExpression(VHDLModel_NorExpression): self._leftOperand = left self._rightOperand = right + @export class XorExpression(VHDLModel_XorExpression): def __init__(self, left: Expression, right: Expression): @@ -202,6 +223,7 @@ class XorExpression(VHDLModel_XorExpression): self._leftOperand = left self._rightOperand = right + @export class XnorExpression(VHDLModel_XnorExpression): def __init__(self, left: Expression, right: Expression): @@ -209,6 +231,7 @@ class XnorExpression(VHDLModel_XnorExpression): self._leftOperand = left self._rightOperand = right + @export class EqualExpression(VHDLModel_EqualExpression): def __init__(self, left: Expression, right: Expression): @@ -216,6 +239,7 @@ class EqualExpression(VHDLModel_EqualExpression): self._leftOperand = left self._rightOperand = right + @export class UnequalExpression(VHDLModel_UnequalExpression): def __init__(self, left: Expression, right: Expression): @@ -223,6 +247,7 @@ class UnequalExpression(VHDLModel_UnequalExpression): self._leftOperand = left self._rightOperand = right + @export class GreaterThanExpression(VHDLModel_GreaterThanExpression): def __init__(self, left: Expression, right: Expression): @@ -230,6 +255,7 @@ class GreaterThanExpression(VHDLModel_GreaterThanExpression): self._leftOperand = left self._rightOperand = right + @export class GreaterEqualExpression(VHDLModel_GreaterEqualExpression): def __init__(self, left: Expression, right: Expression): @@ -237,6 +263,7 @@ class GreaterEqualExpression(VHDLModel_GreaterEqualExpression): self._leftOperand = left self._rightOperand = right + @export class LessThanExpression(VHDLModel_LessThanExpression): def __init__(self, left: Expression, right: Expression): @@ -244,6 +271,7 @@ class LessThanExpression(VHDLModel_LessThanExpression): self._leftOperand = left self._rightOperand = right + @export class ShiftRightLogicExpression(VHDLModel_ShiftRightLogicExpression): def __init__(self, left: Expression, right: Expression): @@ -251,6 +279,7 @@ class ShiftRightLogicExpression(VHDLModel_ShiftRightLogicExpression): self._leftOperand = left self._rightOperand = right + @export class ShiftLeftLogicExpression(VHDLModel_ShiftLeftLogicExpression): def __init__(self, left: Expression, right: Expression): @@ -258,6 +287,7 @@ class ShiftLeftLogicExpression(VHDLModel_ShiftLeftLogicExpression): self._leftOperand = left self._rightOperand = right + @export class ShiftRightArithmeticExpression(VHDLModel_ShiftRightArithmeticExpression): def __init__(self, left: Expression, right: Expression): @@ -265,6 +295,7 @@ class ShiftRightArithmeticExpression(VHDLModel_ShiftRightArithmeticExpression): self._leftOperand = left self._rightOperand = right + @export class ShiftLeftArithmeticExpression(VHDLModel_ShiftLeftArithmeticExpression): def __init__(self, left: Expression, right: Expression): @@ -272,6 +303,7 @@ class ShiftLeftArithmeticExpression(VHDLModel_ShiftLeftArithmeticExpression): self._leftOperand = left self._rightOperand = right + @export class RotateRightExpression(VHDLModel_RotateRightExpression): def __init__(self, left: Expression, right: Expression): @@ -279,6 +311,7 @@ class RotateRightExpression(VHDLModel_RotateRightExpression): self._leftOperand = left self._rightOperand = right + @export class RotateLeftExpression(VHDLModel_RotateLeftExpression): def __init__(self, left: Expression, right: Expression): |