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-rw-r--r--testsuite/gna/issue2381/test.vhdl27
-rwxr-xr-xtestsuite/gna/issue2381/testsuite.sh11
2 files changed, 38 insertions, 0 deletions
diff --git a/testsuite/gna/issue2381/test.vhdl b/testsuite/gna/issue2381/test.vhdl
new file mode 100644
index 000000000..6dd777816
--- /dev/null
+++ b/testsuite/gna/issue2381/test.vhdl
@@ -0,0 +1,27 @@
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity test is
+end entity;
+
+architecture rtl of test is
+ signal a,b,c,d,e: std_logic;
+begin
+
+ COMBINATORIC: process( all ) is
+ begin
+ case a is
+ when '0' =>
+ with b select c <=
+ '0' when '1',
+ '1' when '0',
+ '0' when others;
+ when others =>
+ null;
+ end case;
+ end process;
+
+end architecture rtl;
diff --git a/testsuite/gna/issue2381/testsuite.sh b/testsuite/gna/issue2381/testsuite.sh
new file mode 100755
index 000000000..1d84c0f57
--- /dev/null
+++ b/testsuite/gna/issue2381/testsuite.sh
@@ -0,0 +1,11 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+export GHDL_STD_FLAGS=--std=08
+analyze test.vhdl
+elab_simulate test
+
+clean
+
+echo "Test successful"