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| author | Patrick Lehmann <Patrick.Lehmann@plc2.de> | 2021-08-16 17:43:29 +0200 |
|---|---|---|
| committer | umarcor <unai.martinezcorral@ehu.eus> | 2021-08-23 16:35:36 +0200 |
| commit | c74c26bbb6b58e0cf7fba78e382f0949240b7721 (patch) | |
| tree | 00537a747112a41c82cd4daf3673fd4b6caa19bb /testsuite | |
| parent | 2daa121cd8d40175a82c887b514208ff7f0a50da (diff) | |
| download | ghdl-c74c26bbb6b58e0cf7fba78e382f0949240b7721.tar.gz ghdl-c74c26bbb6b58e0cf7fba78e382f0949240b7721.tar.bz2 ghdl-c74c26bbb6b58e0cf7fba78e382f0949240b7721.zip | |
Handle if-statements.
Diffstat (limited to 'testsuite')
| -rw-r--r-- | testsuite/pyunit/Current.vhdl | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/testsuite/pyunit/Current.vhdl b/testsuite/pyunit/Current.vhdl index f755b95a8..cd6537519 100644 --- a/testsuite/pyunit/Current.vhdl +++ b/testsuite/pyunit/Current.vhdl @@ -90,6 +90,8 @@ begin if rising_edge(Clock) then if Reset = '1' then Q <= (others => '0'); + elsif Load = '1' then + Q <= D after 10 ns; else Q <= std_logic_vector(unsigned(Q) + 1); end if; |