From c74c26bbb6b58e0cf7fba78e382f0949240b7721 Mon Sep 17 00:00:00 2001
From: Patrick Lehmann <Patrick.Lehmann@plc2.de>
Date: Mon, 16 Aug 2021 17:43:29 +0200
Subject: Handle if-statements.

---
 testsuite/pyunit/Current.vhdl | 2 ++
 1 file changed, 2 insertions(+)

(limited to 'testsuite')

diff --git a/testsuite/pyunit/Current.vhdl b/testsuite/pyunit/Current.vhdl
index f755b95a8..cd6537519 100644
--- a/testsuite/pyunit/Current.vhdl
+++ b/testsuite/pyunit/Current.vhdl
@@ -90,6 +90,8 @@ begin
 		if rising_edge(Clock) then
 			if Reset = '1' then
 				Q <= (others => '0');
+			elsif Load = '1' then
+				Q <= D after 10 ns;
 			else
 				Q <= std_logic_vector(unsigned(Q) + 1);
 			end if;
-- 
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