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author | Tristan Gingold <tgingold@free.fr> | 2014-10-29 20:36:02 +0100 |
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committer | Tristan Gingold <tgingold@free.fr> | 2014-10-29 20:36:02 +0100 |
commit | 236a876a8448b89061bb71869c36a68aea0199c3 (patch) | |
tree | 36f03ad7f2b9a5eec72f3c635f90228f84696cbd /testsuite | |
parent | e00d31baa0e7190b959cfb03df03b260e402da05 (diff) | |
download | ghdl-236a876a8448b89061bb71869c36a68aea0199c3.tar.gz ghdl-236a876a8448b89061bb71869c36a68aea0199c3.tar.bz2 ghdl-236a876a8448b89061bb71869c36a68aea0199c3.zip |
Add testcase for bug 22868.
Diffstat (limited to 'testsuite')
-rw-r--r-- | testsuite/gna/bug22868/Makefile | 15 | ||||
-rw-r--r-- | testsuite/gna/bug22868/NOTES | 9 | ||||
-rw-r--r-- | testsuite/gna/bug22868/fails1.vhdl | 31 | ||||
-rw-r--r-- | testsuite/gna/bug22868/fails2.vhdl | 28 | ||||
-rwxr-xr-x | testsuite/gna/bug22868/testsuite.sh | 10 | ||||
-rw-r--r-- | testsuite/gna/bug22868/works.vhdl | 39 |
6 files changed, 132 insertions, 0 deletions
diff --git a/testsuite/gna/bug22868/Makefile b/testsuite/gna/bug22868/Makefile new file mode 100644 index 000000000..328c08c6b --- /dev/null +++ b/testsuite/gna/bug22868/Makefile @@ -0,0 +1,15 @@ +.PHONY: default +default: + -make works.o + -make fails1.o + -make fails2.o + + +%.o: %.vhdl + ghdl -a $< + +.PHONY: clean +clean: + ghdl --clean + rm *.cf + diff --git a/testsuite/gna/bug22868/NOTES b/testsuite/gna/bug22868/NOTES new file mode 100644 index 000000000..bef147179 --- /dev/null +++ b/testsuite/gna/bug22868/NOTES @@ -0,0 +1,9 @@ +I think these are the most stripped down examples I could figure out, +and the gist of it seems to be that it has to do with splitting the +right hand side of a port map by amounts that are not known at +elaboration time...or something like that. In fails2.vhdl the +variable isn't declared anywhere, but it still crashes with the +bug notice, rather than just failing with an error message. + +works.vhdl is provided for contrast, i.e. generics are used +except for the specific line that would cause it to crash. diff --git a/testsuite/gna/bug22868/fails1.vhdl b/testsuite/gna/bug22868/fails1.vhdl new file mode 100644 index 000000000..7bd3a9192 --- /dev/null +++ b/testsuite/gna/bug22868/fails1.vhdl @@ -0,0 +1,31 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity fails1 is + generic ( + w : integer := 8 + ); + port( + x : in std_logic; + y : out std_logic_vector(7 downto 0); + z : out std_logic + ); +end entity; + +architecture a of fails1 is + component subcomponent is + port( + x : in std_logic; + y : out std_logic_vector(8 downto 0) + ); + end component; +begin + + s : subcomponent + port map( + x => x, + y(w downto 1) => y, + y(0) => z + ); + +end a; diff --git a/testsuite/gna/bug22868/fails2.vhdl b/testsuite/gna/bug22868/fails2.vhdl new file mode 100644 index 000000000..57819f9cf --- /dev/null +++ b/testsuite/gna/bug22868/fails2.vhdl @@ -0,0 +1,28 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity fails2 is + port( + x : in std_logic; + y : out std_logic_vector(7 downto 0); + z : out std_logic + ); +end fails2; + +architecture a of fails2 is + component subcomponent is + port( + x : in std_logic; + y : out std_logic_vector(8 downto 0) + ); + end component; +begin + + s : subcomponent + port map( + x => x, + y(cheese downto 1) => y, + y(0) => z + ); + +end a; diff --git a/testsuite/gna/bug22868/testsuite.sh b/testsuite/gna/bug22868/testsuite.sh new file mode 100755 index 000000000..6b3dc4f19 --- /dev/null +++ b/testsuite/gna/bug22868/testsuite.sh @@ -0,0 +1,10 @@ +#! /bin/sh + +. ../../testenv.sh + +analyze_failure fails1.vhdl +analyze_failure fails2.vhdl +analyze works.vhdl +clean + +echo "Test successful" diff --git a/testsuite/gna/bug22868/works.vhdl b/testsuite/gna/bug22868/works.vhdl new file mode 100644 index 000000000..bf1cef7e3 --- /dev/null +++ b/testsuite/gna/bug22868/works.vhdl @@ -0,0 +1,39 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity works is + generic ( + width : integer := 8 + ); + port( + x : in std_logic; + y : out std_logic_vector(width-1 downto 0); + z : out std_logic + ); +end works; + +architecture a of works is + component subcomponent is + generic ( + w : integer + ); + port( + x : in std_logic; + y : out std_logic_vector(w-1 downto 0) + ); + end component; +begin + + s : subcomponent + generic map( + w => width+1 + ) + port map( + x => x, + y(8 downto 1) => y, + y(0) => z + ); + +end a; + + |