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author | Tristan Gingold <tgingold@free.fr> | 2019-12-04 07:39:28 +0100 |
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committer | Tristan Gingold <tgingold@free.fr> | 2019-12-04 07:39:28 +0100 |
commit | 0b8470075bc3b1285abc18d78428779fc671573d (patch) | |
tree | 9d541ca09576f33c2f76d5f1649e44be7f5c730c /testsuite/synth | |
parent | 4bc83fa410542b3c6a9c122d1051dfdcd9a2daa1 (diff) | |
download | ghdl-0b8470075bc3b1285abc18d78428779fc671573d.tar.gz ghdl-0b8470075bc3b1285abc18d78428779fc671573d.tar.bz2 ghdl-0b8470075bc3b1285abc18d78428779fc671573d.zip |
testsuite: add test for #1050
Diffstat (limited to 'testsuite/synth')
-rwxr-xr-x | testsuite/synth/issue1050/testsuite.sh | 11 | ||||
-rw-r--r-- | testsuite/synth/issue1050/top.vhdl | 36 |
2 files changed, 47 insertions, 0 deletions
diff --git a/testsuite/synth/issue1050/testsuite.sh b/testsuite/synth/issue1050/testsuite.sh new file mode 100755 index 000000000..98143a52e --- /dev/null +++ b/testsuite/synth/issue1050/testsuite.sh @@ -0,0 +1,11 @@ +#! /bin/sh + +. ../../testenv.sh + +for t in top; do + synth $t.vhdl -e $t > syn_$t.vhdl + analyze syn_$t.vhdl + clean +done + +echo "Test successful" diff --git a/testsuite/synth/issue1050/top.vhdl b/testsuite/synth/issue1050/top.vhdl new file mode 100644 index 000000000..23a9e2ff3 --- /dev/null +++ b/testsuite/synth/issue1050/top.vhdl @@ -0,0 +1,36 @@ +library ieee; +use ieee.std_logic_1164.ALL; + +entity child is + port ( + O1: out std_logic; + O2: out std_logic + ); +end entity child; + +architecture rtl of child is +begin + O1 <= '0'; + O2 <= '1'; +end architecture rtl; + + +library ieee; +use ieee.std_logic_1164.ALL; + +entity top is + port ( + O: out std_logic + ); +end entity top; + +architecture rtl of top is + component child is + port ( + O1: out std_logic; + O2: out std_logic + ); + end component child; +begin + inst : child port map(O1 => O); +end architecture rtl; |