2 files changed, 47 insertions, 0 deletions
diff --git a/testsuite/synth/issue1050/testsuite.sh b/testsuite/synth/issue1050/testsuite.sh
new file mode 100755
index 000000000..98143a52e
--- /dev/null
+++ b/testsuite/synth/issue1050/testsuite.sh
@@ -0,0 +1,11 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+for t in top; do
+    synth $t.vhdl -e $t > syn_$t.vhdl
+    analyze syn_$t.vhdl
+    clean
+done
+
+echo "Test successful"
diff --git a/testsuite/synth/issue1050/top.vhdl b/testsuite/synth/issue1050/top.vhdl
new file mode 100644
index 000000000..23a9e2ff3
--- /dev/null
+++ b/testsuite/synth/issue1050/top.vhdl
@@ -0,0 +1,36 @@
+library ieee;
+use ieee.std_logic_1164.ALL;
+
+entity child is
+  port (
+    O1: out std_logic;
+    O2: out std_logic
+  );
+end entity child;
+
+architecture rtl of child is
+begin
+  O1 <= '0';
+  O2 <= '1';
+end architecture rtl;
+
+
+library ieee;
+use ieee.std_logic_1164.ALL;
+
+entity top is
+  port (
+    O: out std_logic
+  );
+end entity top;
+
+architecture rtl of top is
+  component child is
+    port (
+      O1: out std_logic;
+      O2: out std_logic
+    );
+  end component child;
+begin
+  inst : child port map(O1 => O);
+end architecture rtl;