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authorTristan Gingold <tgingold@free.fr>2019-09-17 18:32:12 +0200
committerTristan Gingold <tgingold@free.fr>2019-09-17 18:32:12 +0200
commiteb3d32a6de8822eb87a6bfd72dc1c94f9ff9a107 (patch)
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parent163a73a3501cb9f34025c3def6665cf161d744dc (diff)
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Add missing file for previous commit.
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diff --git a/testsuite/synth/var01/var06.vhdl b/testsuite/synth/var01/var06.vhdl
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+library ieee;
+use ieee.std_logic_1164.all;
+
+entity var06 is
+ port (mask : std_logic_vector (1 downto 0);
+ val : std_logic_vector (15 downto 0);
+ res : out std_logic_vector (15 downto 0));
+end var06;
+
+architecture behav of var06 is
+begin
+ process (all)
+ variable t : std_logic_vector (15 downto 0);
+ begin
+ t := (others => '0');
+ if mask (0) = '1' then
+ t (7 downto 0) := val (7 downto 0);
+ end if;
+ if mask (1) = '1' then
+ t (15 downto 8) := val (15 downto 8);
+ end if;
+ res <= t;
+ end process;
+end behav;