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author | Tristan Gingold <tgingold@free.fr> | 2019-09-17 18:32:12 +0200 |
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committer | Tristan Gingold <tgingold@free.fr> | 2019-09-17 18:32:12 +0200 |
commit | eb3d32a6de8822eb87a6bfd72dc1c94f9ff9a107 (patch) | |
tree | d86fbc2d83d74dd1068daca870efd4f53b44432f /testsuite/synth/var01/var06.vhdl | |
parent | 163a73a3501cb9f34025c3def6665cf161d744dc (diff) | |
download | ghdl-eb3d32a6de8822eb87a6bfd72dc1c94f9ff9a107.tar.gz ghdl-eb3d32a6de8822eb87a6bfd72dc1c94f9ff9a107.tar.bz2 ghdl-eb3d32a6de8822eb87a6bfd72dc1c94f9ff9a107.zip |
Add missing file for previous commit.
Diffstat (limited to 'testsuite/synth/var01/var06.vhdl')
-rw-r--r-- | testsuite/synth/var01/var06.vhdl | 24 |
1 files changed, 24 insertions, 0 deletions
diff --git a/testsuite/synth/var01/var06.vhdl b/testsuite/synth/var01/var06.vhdl new file mode 100644 index 000000000..ca7f103b2 --- /dev/null +++ b/testsuite/synth/var01/var06.vhdl @@ -0,0 +1,24 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity var06 is + port (mask : std_logic_vector (1 downto 0); + val : std_logic_vector (15 downto 0); + res : out std_logic_vector (15 downto 0)); +end var06; + +architecture behav of var06 is +begin + process (all) + variable t : std_logic_vector (15 downto 0); + begin + t := (others => '0'); + if mask (0) = '1' then + t (7 downto 0) := val (7 downto 0); + end if; + if mask (1) = '1' then + t (15 downto 8) := val (15 downto 8); + end if; + res <= t; + end process; +end behav; |