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author | Tristan Gingold <tgingold@free.fr> | 2019-11-03 07:40:18 +0100 |
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committer | Tristan Gingold <tgingold@free.fr> | 2019-11-03 21:15:07 +0100 |
commit | f9102057180443575edcebe71edb6c3eb1fc571d (patch) | |
tree | fb79fd04913dc1bbc5f569ea842c20339b2e436d /testsuite/synth/var01/var01b.vhdl | |
parent | 79c615e88dd652d7f2077ccdbef0487d74febd98 (diff) | |
download | ghdl-f9102057180443575edcebe71edb6c3eb1fc571d.tar.gz ghdl-f9102057180443575edcebe71edb6c3eb1fc571d.tar.bz2 ghdl-f9102057180443575edcebe71edb6c3eb1fc571d.zip |
testsuite/synth/var01: add more tests.
Diffstat (limited to 'testsuite/synth/var01/var01b.vhdl')
-rw-r--r-- | testsuite/synth/var01/var01b.vhdl | 26 |
1 files changed, 26 insertions, 0 deletions
diff --git a/testsuite/synth/var01/var01b.vhdl b/testsuite/synth/var01/var01b.vhdl new file mode 100644 index 000000000..a494a0341 --- /dev/null +++ b/testsuite/synth/var01/var01b.vhdl @@ -0,0 +1,26 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity var01b is + port (clk : std_logic; + mask : std_logic_vector (1 downto 0); + val : std_logic_vector (3 downto 0); + res : out std_logic_vector (3 downto 0)); +end var01b; + +architecture behav of var01b is +begin + process (clk) + variable hi, lo : natural; + begin + if rising_edge (clk) then + for i in 0 to 1 loop + if mask (i) = '1' then + lo := i * 2; + hi := lo + 1; + res (hi downto lo) <= val (hi downto lo); + end if; + end loop; + end if; + end process; +end behav; |