testsuite/synth/var01: add more tests.

8 files changed, 233 insertions, 2 deletions

diff --git a/testsuite/synth/var01/tb_var01.vhdl b/testsuite/synth/var01/tb_var01.vhdl
index 48dca33a3..a21838f17 100644
--- a/testsuite/synth/var01/tb_var01.vhdl
+++ b/testsuite/synth/var01/tb_var01.vhdl
@@ -29,7 +29,7 @@ begin
     mask <= x"f";
     val <= x"12_34_56_78";
     pulse;
-    assert res = x"12_34_56_78" severity failure;
+    assert res = x"12_34_56_78" report "res=" & to_hstring (res) severity failure;
     
     mask <= x"8";
     val <= x"9a_00_00_00";
diff --git a/testsuite/synth/var01/tb_var01a.vhdl b/testsuite/synth/var01/tb_var01a.vhdl
new file mode 100644
index 000000000..3712f1d8b
--- /dev/null
+++ b/testsuite/synth/var01/tb_var01a.vhdl
@@ -0,0 +1,51 @@
+entity tb_var01a is
+end tb_var01a;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tb_var01a is
+  signal clk : std_logic;
+  signal mask : std_logic_vector (1 downto 0);
+  signal val : std_logic_vector (7 downto 0);
+  signal res : std_logic_vector (7 downto 0);
+begin
+  dut: entity work.var01a
+    port map (
+      clk => clk,
+      mask => mask,
+      val => val,
+      res => res);
+
+  process
+    procedure pulse is
+    begin
+      clk <= '0';
+      wait for 1 ns;
+      clk <= '1';
+      wait for 1 ns;
+    end pulse;
+  begin
+    mask <= "11";
+    val <= x"12";
+    pulse;
+    assert res = x"12" report "res=" & to_hstring (res) severity failure;
+    
+    mask <= "10";
+    val <= x"9a";
+    pulse;
+    assert res = x"92" severity failure;
+
+    mask <= "00";
+    val <= x"00";
+    pulse;
+    assert res = x"92" severity failure;
+
+    mask <= "01";
+    val <= x"de";
+    pulse;
+    assert res = x"9e" severity failure;
+
+    wait;
+  end process;
+end behav;
diff --git a/testsuite/synth/var01/tb_var01b.vhdl b/testsuite/synth/var01/tb_var01b.vhdl
new file mode 100644
index 000000000..6d5e9e395
--- /dev/null
+++ b/testsuite/synth/var01/tb_var01b.vhdl
@@ -0,0 +1,51 @@
+entity tb_var01b is
+end tb_var01b;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tb_var01b is
+  signal clk : std_logic;
+  signal mask : std_logic_vector (1 downto 0);
+  signal val : std_logic_vector (3 downto 0);
+  signal res : std_logic_vector (3 downto 0);
+begin
+  dut: entity work.var01b
+    port map (
+      clk => clk,
+      mask => mask,
+      val => val,
+      res => res);
+
+  process
+    procedure pulse is
+    begin
+      clk <= '0';
+      wait for 1 ns;
+      clk <= '1';
+      wait for 1 ns;
+    end pulse;
+  begin
+    mask <= "11";
+    val <= b"00_01";
+    pulse;
+    assert res = b"00_01" report "res=" & to_bstring (res) severity failure;
+
+    mask <= "10";
+    val <= b"11_00";
+    pulse;
+    assert res = b"11_01" severity failure;
+
+    mask <= "00";
+    val <= b"00_00";
+    pulse;
+    assert res = b"11_01" severity failure;
+
+    mask <= "01";
+    val <= b"00_10";
+    pulse;
+    assert res = b"11_10" severity failure;
+
+    wait;
+  end process;
+end behav;
diff --git a/testsuite/synth/var01/tb_var01c.vhdl b/testsuite/synth/var01/tb_var01c.vhdl
new file mode 100644
index 000000000..f0c33a19d
--- /dev/null
+++ b/testsuite/synth/var01/tb_var01c.vhdl
@@ -0,0 +1,51 @@
+entity tb_var01c is
+end tb_var01c;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tb_var01c is
+  signal clk : std_logic;
+  signal mask : std_logic_vector (1 downto 0);
+  signal val : std_logic_vector (1 downto 0);
+  signal res : std_logic_vector (3 downto 0);
+begin
+  dut: entity work.var01c
+    port map (
+      clk => clk,
+      mask => mask,
+      val => val,
+      res => res);
+
+  process
+    procedure pulse is
+    begin
+      clk <= '0';
+      wait for 1 ns;
+      clk <= '1';
+      wait for 1 ns;
+    end pulse;
+  begin
+    mask <= "11";
+    val <= b"01";
+    pulse;
+    assert res = b"01_01" report "res=" & to_bstring (res) severity failure;
+
+    mask <= "10";
+    val <= b"11";
+    pulse;
+    assert res = b"11_01" severity failure;
+
+    mask <= "00";
+    val <= b"00";
+    pulse;
+    assert res = b"11_01" severity failure;
+
+    mask <= "01";
+    val <= b"10";
+    pulse;
+    assert res = b"11_10" severity failure;
+
+    wait;
+  end process;
+end behav;
diff --git a/testsuite/synth/var01/testsuite.sh b/testsuite/synth/var01/testsuite.sh
index bd1b9d4f5..d2c9c167c 100755
--- a/testsuite/synth/var01/testsuite.sh
+++ b/testsuite/synth/var01/testsuite.sh
@@ -4,7 +4,7 @@
 
 GHDL_STD_FLAGS=--std=08
 
-for t in var01 var02 var03 var04 var05 var06; do
+for t in var01c var01b var01a var01 var02 var03 var04 var05 var06; do
     analyze $t.vhdl tb_$t.vhdl
     elab_simulate tb_$t
     clean
diff --git a/testsuite/synth/var01/var01a.vhdl b/testsuite/synth/var01/var01a.vhdl
new file mode 100644
index 000000000..7cb4018da
--- /dev/null
+++ b/testsuite/synth/var01/var01a.vhdl
@@ -0,0 +1,26 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity var01a is
+  port (clk : std_logic;
+        mask : std_logic_vector (1 downto 0);
+        val : std_logic_vector (7 downto 0);
+        res : out std_logic_vector (7 downto 0));
+end var01a;
+
+architecture behav of var01a is
+begin
+  process (clk)
+    variable hi, lo : natural;
+  begin
+    if rising_edge (clk) then
+      for i in 0 to 1 loop
+        if mask (i) = '1' then
+          lo := i * 4;
+          hi := lo + 3;
+          res (hi downto lo) <= val (hi downto lo);
+        end if;
+      end loop;
+    end if;
+  end process;
+end behav;
diff --git a/testsuite/synth/var01/var01b.vhdl b/testsuite/synth/var01/var01b.vhdl
new file mode 100644
index 000000000..a494a0341
--- /dev/null
+++ b/testsuite/synth/var01/var01b.vhdl
@@ -0,0 +1,26 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity var01b is
+  port (clk : std_logic;
+        mask : std_logic_vector (1 downto 0);
+        val : std_logic_vector (3 downto 0);
+        res : out std_logic_vector (3 downto 0));
+end var01b;
+
+architecture behav of var01b is
+begin
+  process (clk)
+    variable hi, lo : natural;
+  begin
+    if rising_edge (clk) then
+      for i in 0 to 1 loop
+        if mask (i) = '1' then
+          lo := i * 2;
+          hi := lo + 1;
+          res (hi downto lo) <= val (hi downto lo);
+        end if;
+      end loop;
+    end if;
+  end process;
+end behav;
diff --git a/testsuite/synth/var01/var01c.vhdl b/testsuite/synth/var01/var01c.vhdl
new file mode 100644
index 000000000..35f688c6b
--- /dev/null
+++ b/testsuite/synth/var01/var01c.vhdl
@@ -0,0 +1,26 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity var01c is
+  port (clk : std_logic;
+        mask : std_logic_vector (1 downto 0);
+        val : std_logic_vector (1 downto 0);
+        res : out std_logic_vector (3 downto 0));
+end var01c;
+
+architecture behav of var01c is
+begin
+  process (clk)
+    variable hi, lo : natural;
+  begin
+    if rising_edge (clk) then
+      for i in 0 to 1 loop
+        if mask (i) = '1' then
+          lo := i * 2;
+          hi := lo + 1;
+          res (hi downto lo) <= val;
+        end if;
+      end loop;
+    end if;
+  end process;
+end behav;