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author | Tristan Gingold <tgingold@free.fr> | 2019-11-03 07:42:21 +0100 |
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committer | Tristan Gingold <tgingold@free.fr> | 2019-11-03 21:15:08 +0100 |
commit | 2170c6f1592156b51254f30e2c4d0019fc91855b (patch) | |
tree | cc51e2435b637b37e100959efdf9bf59b6480757 /testsuite/synth/synth56/tb_test2.vhdl | |
parent | 7c81c5a02e0d2eabab6aa90405dd947302e68674 (diff) | |
download | ghdl-2170c6f1592156b51254f30e2c4d0019fc91855b.tar.gz ghdl-2170c6f1592156b51254f30e2c4d0019fc91855b.tar.bz2 ghdl-2170c6f1592156b51254f30e2c4d0019fc91855b.zip |
testsuite/synth: add test for tgingold/ghdlsynth-beta#56
Diffstat (limited to 'testsuite/synth/synth56/tb_test2.vhdl')
-rw-r--r-- | testsuite/synth/synth56/tb_test2.vhdl | 26 |
1 files changed, 26 insertions, 0 deletions
diff --git a/testsuite/synth/synth56/tb_test2.vhdl b/testsuite/synth/synth56/tb_test2.vhdl new file mode 100644 index 000000000..3403d30db --- /dev/null +++ b/testsuite/synth/synth56/tb_test2.vhdl @@ -0,0 +1,26 @@ +entity tb_test2 is +end tb_test2; + +library ieee; +use ieee.std_logic_1164.all; + +architecture behav of tb_test2 is + signal v : std_logic_vector(1 downto 0); + signal s : std_logic_vector(1 downto 0); +begin + dut: entity work.test2 + port map (s, v); + + process + begin + s <= "00"; + wait for 1 ns; + assert v = "00" severity failure; + + s <= "11"; + wait for 1 ns; + assert v = "10" severity failure; + + wait; + end process; +end behav; |