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authorTristan Gingold <tgingold@free.fr>2019-11-03 07:42:21 +0100
committerTristan Gingold <tgingold@free.fr>2019-11-03 21:15:08 +0100
commit2170c6f1592156b51254f30e2c4d0019fc91855b (patch)
treecc51e2435b637b37e100959efdf9bf59b6480757 /testsuite/synth/synth56/tb_test2.vhdl
parent7c81c5a02e0d2eabab6aa90405dd947302e68674 (diff)
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testsuite/synth: add test for tgingold/ghdlsynth-beta#56
Diffstat (limited to 'testsuite/synth/synth56/tb_test2.vhdl')
-rw-r--r--testsuite/synth/synth56/tb_test2.vhdl26
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diff --git a/testsuite/synth/synth56/tb_test2.vhdl b/testsuite/synth/synth56/tb_test2.vhdl
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+++ b/testsuite/synth/synth56/tb_test2.vhdl
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+entity tb_test2 is
+end tb_test2;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tb_test2 is
+ signal v : std_logic_vector(1 downto 0);
+ signal s : std_logic_vector(1 downto 0);
+begin
+ dut: entity work.test2
+ port map (s, v);
+
+ process
+ begin
+ s <= "00";
+ wait for 1 ns;
+ assert v = "00" severity failure;
+
+ s <= "11";
+ wait for 1 ns;
+ assert v = "10" severity failure;
+
+ wait;
+ end process;
+end behav;