From 2170c6f1592156b51254f30e2c4d0019fc91855b Mon Sep 17 00:00:00 2001 From: Tristan Gingold Date: Sun, 3 Nov 2019 07:42:21 +0100 Subject: testsuite/synth: add test for tgingold/ghdlsynth-beta#56 --- testsuite/synth/synth56/tb_test2.vhdl | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) create mode 100644 testsuite/synth/synth56/tb_test2.vhdl (limited to 'testsuite/synth/synth56/tb_test2.vhdl') diff --git a/testsuite/synth/synth56/tb_test2.vhdl b/testsuite/synth/synth56/tb_test2.vhdl new file mode 100644 index 000000000..3403d30db --- /dev/null +++ b/testsuite/synth/synth56/tb_test2.vhdl @@ -0,0 +1,26 @@ +entity tb_test2 is +end tb_test2; + +library ieee; +use ieee.std_logic_1164.all; + +architecture behav of tb_test2 is + signal v : std_logic_vector(1 downto 0); + signal s : std_logic_vector(1 downto 0); +begin + dut: entity work.test2 + port map (s, v); + + process + begin + s <= "00"; + wait for 1 ns; + assert v = "00" severity failure; + + s <= "11"; + wait for 1 ns; + assert v = "10" severity failure; + + wait; + end process; +end behav; -- cgit v1.2.3