testsuite/synth: add a test for ghdl/ghdl-yosys-plugin#115

3 files changed, 82 insertions, 0 deletions

diff --git a/testsuite/synth/synth115/tb_testcase.vhdl b/testsuite/synth/synth115/tb_testcase.vhdl
new file mode 100644
index 000000000..620447134
--- /dev/null
+++ b/testsuite/synth/synth115/tb_testcase.vhdl
@@ -0,0 +1,34 @@
+entity tb_testcase is
+end tb_testcase;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tb_testcase is
+  signal din  : std_logic_vector (3 downto 0);
+  signal dout : std_logic_vector (1 downto 0);
+begin
+  dut: entity work.testcase
+    port map (din, dout);
+
+  process
+  begin
+    din <= "0001";
+    wait for 1 ns;
+    assert dout = "01" severity failure;
+
+    din <= "0010";
+    wait for 1 ns;
+    assert dout = "10" severity failure;
+
+    din <= "1010";
+    wait for 1 ns;
+    assert dout = "01" severity failure;
+
+    din <= "1001";
+    wait for 1 ns;
+    assert dout = "00" severity failure;
+
+    wait;
+  end process;
+end behav;
diff --git a/testsuite/synth/synth115/testcase.vhdl b/testsuite/synth/synth115/testcase.vhdl
new file mode 100644
index 000000000..e157e326a
--- /dev/null
+++ b/testsuite/synth/synth115/testcase.vhdl
@@ -0,0 +1,41 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity testcase is
+   port (
+          din    : in  std_logic_vector(3 downto 0);
+          dout   : out std_logic_vector(1 downto 0)
+        );
+end testcase;
+
+architecture behavior of testcase is
+   signal testidx : natural range 3 downto 2;
+begin
+
+--------------------------------------------------------------
+-- tc0 does not cause an overflow error
+--tc0: process(din)
+--     begin
+--        if (din(3)='1') then
+--           dout <= din(2 downto 1);
+--        else
+--           dout <= din(1 downto 0);
+--        end if;
+--     end process;
+--------------------------------------------------------------
+
+--------------------------------------------------------------
+-- tc1 with the dout assignment does cause an overflow error
+tc1: process(din)
+     begin
+        if (din(3)='1') then
+           testidx <= 3;
+        else
+           testidx <= 2;
+        end if;
+     end process;
+
+   dout   <= din(testidx-1 downto testidx-dout'length);
+--------------------------------------------------------------
+
+end behavior;
diff --git a/testsuite/synth/synth115/testsuite.sh b/testsuite/synth/synth115/testsuite.sh
new file mode 100755
index 000000000..d5dd83e3e
--- /dev/null
+++ b/testsuite/synth/synth115/testsuite.sh
@@ -0,0 +1,7 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+synth_tb testcase
+
+echo "Test successful"