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authorTristan Gingold <tgingold@free.fr>2020-05-09 18:32:41 +0200
committerTristan Gingold <tgingold@free.fr>2020-05-09 18:32:41 +0200
commit06202188e0e88c0096518415413c08bd0471644b (patch)
tree088ba5316602b01c9d2cedbfc6f6b37952b4b521 /testsuite/synth/synth104/tb_case02.vhdl
parent894bbd7c174bafd59fbea3b3bd990ffdfbb685d2 (diff)
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testsuite/synth: add a test for ghdl/ghdl-yosys-plugin#104
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-rw-r--r--testsuite/synth/synth104/tb_case02.vhdl39
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diff --git a/testsuite/synth/synth104/tb_case02.vhdl b/testsuite/synth/synth104/tb_case02.vhdl
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+entity tb_case02 is
+end tb_case02;
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+architecture behav of tb_case02 is
+ signal sel : unsigned (3 downto 0);
+ signal det : std_logic_vector (1 downto 0);
+begin
+ dut: entity work.case02
+ port map (sel, det);
+
+ process
+ begin
+ sel <= "0000";
+ wait for 1 ns;
+ assert det = "00" severity failure;
+
+ sel <= "0010";
+ wait for 1 ns;
+ assert det = "01" severity failure;
+
+ sel <= "0110";
+ wait for 1 ns;
+ assert det = "01" severity failure;
+
+ sel <= "1010";
+ wait for 1 ns;
+ assert det = "10" severity failure;
+
+ sel <= "1111";
+ wait for 1 ns;
+ assert det = "11" severity failure;
+
+ wait;
+ end process;
+end behav;