testsuite/synth: add tests for std_logic_misc reduce functions

4 files changed, 90 insertions, 16 deletions

diff --git a/testsuite/synth/sns01/reduce.vhdl b/testsuite/synth/sns01/reduce.vhdl
new file mode 100644
index 000000000..5d1ace974
--- /dev/null
+++ b/testsuite/synth/sns01/reduce.vhdl
@@ -0,0 +1,23 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_misc.all;
+
+entity reduce is
+  port (vec : std_logic_vector(7 downto 0);
+        res_and : out std_logic;
+        res_nand : out std_logic;
+        res_or : out std_logic;
+        res_nor : out std_logic;
+        res_xor : out std_logic;
+        res_xnor : out std_logic);
+end reduce;
+
+architecture behav of reduce is
+begin
+  res_and <= and_reduce(vec);
+  res_nand <= nand_reduce(vec);
+  res_or <= or_reduce(vec);
+  res_nor <= nor_reduce(vec);
+  res_xor <= xor_reduce(vec);
+  res_xnor <= xnor_reduce(vec);
+end behav;
diff --git a/testsuite/synth/sns01/sns02.vhdl b/testsuite/synth/sns01/sns02.vhdl
deleted file mode 100644
index c68ddbd90..000000000
--- a/testsuite/synth/sns01/sns02.vhdl
+++ /dev/null
@@ -1,13 +0,0 @@
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.std_logic_misc.all;
-
-entity sns02 is
-  port (a : std_logic_vector(7 downto 0);
-        b : out std_logic);
-end sns02;
-
-architecture behav of sns02 is
-begin
-  b <= or_reduce(a);
-end behav;
diff --git a/testsuite/synth/sns01/tb_reduce.vhdl b/testsuite/synth/sns01/tb_reduce.vhdl
new file mode 100644
index 000000000..028638570
--- /dev/null
+++ b/testsuite/synth/sns01/tb_reduce.vhdl
@@ -0,0 +1,66 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_misc.all;
+
+entity tb_reduce is
+end;
+
+architecture behav of tb_reduce is
+  signal vec       : std_logic_vector (7 downto 0);
+  signal res_and   : std_logic;
+  signal res_nand  : std_logic;
+  signal res_or    : std_logic;
+  signal res_nor   : std_logic;
+  signal res_xor   : std_logic;
+  signal res_xnor  : std_logic;
+begin
+  dut: entity work.reduce
+    port map (vec => vec,
+              res_and  => res_and,
+              res_nand => res_nand,
+              res_or   => res_or,
+              res_nor  => res_nor,
+              res_xor  => res_xor,
+              res_xnor => res_xnor);
+
+  process
+  begin
+    vec <= "00000000";
+    wait for 1 ns;
+    assert res_and  = '0' severity failure;
+    assert res_nand = '1' severity failure;
+    assert res_or   = '0' severity failure;
+    assert res_nor  = '1' severity failure;
+    assert res_xor  = '0' severity failure;
+    assert res_xnor = '1' severity failure;
+
+    vec <= "00010000";
+    wait for 1 ns;
+    assert res_and  = '0' severity failure;
+    assert res_nand = '1' severity failure;
+    assert res_or   = '1' severity failure;
+    assert res_nor  = '0' severity failure;
+    assert res_xor  = '1' severity failure;
+    assert res_xnor = '0' severity failure;
+
+    vec <= "00100010";
+    wait for 1 ns;
+    assert res_and  = '0' severity failure;
+    assert res_nand = '1' severity failure;
+    assert res_or   = '1' severity failure;
+    assert res_nor  = '0' severity failure;
+    assert res_xor  = '0' severity failure;
+    assert res_xnor = '1' severity failure;
+
+    vec <= "11111111";
+    wait for 1 ns;
+    assert res_and  = '1' severity failure;
+    assert res_nand = '0' severity failure;
+    assert res_or   = '1' severity failure;
+    assert res_nor  = '0' severity failure;
+    assert res_xor  = '0' severity failure;
+    assert res_xnor = '1' severity failure;
+
+    wait;
+  end process;
+end behav;
diff --git a/testsuite/synth/sns01/testsuite.sh b/testsuite/synth/sns01/testsuite.sh
index 20f3372c6..9d4a21fba 100755
--- a/testsuite/synth/sns01/testsuite.sh
+++ b/testsuite/synth/sns01/testsuite.sh
@@ -25,9 +25,7 @@ for t in sns01; do
     clean
 done
 
-synth_analyze sns02
-clean
-
+synth_tb reduce
 synth_tb add03
 
 echo "Test successful"