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author | Tristan Gingold <tgingold@free.fr> | 2020-12-12 08:19:02 +0100 |
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committer | Tristan Gingold <tgingold@free.fr> | 2020-12-12 11:24:24 +0100 |
commit | 2c20e236a91e7f04d44654eda9d1e54bb074603f (patch) | |
tree | 485fa6b35ae269be5ede963b8670f0a1894a56ff /testsuite/synth/slice01/slice04.vhdl | |
parent | 6eab3c3c5da3ee3df019370389a6ee2a0b4d04c2 (diff) | |
download | ghdl-2c20e236a91e7f04d44654eda9d1e54bb074603f.tar.gz ghdl-2c20e236a91e7f04d44654eda9d1e54bb074603f.tar.bz2 ghdl-2c20e236a91e7f04d44654eda9d1e54bb074603f.zip |
testsuite/synth: add a test for previous commit
Diffstat (limited to 'testsuite/synth/slice01/slice04.vhdl')
-rw-r--r-- | testsuite/synth/slice01/slice04.vhdl | 27 |
1 files changed, 27 insertions, 0 deletions
diff --git a/testsuite/synth/slice01/slice04.vhdl b/testsuite/synth/slice01/slice04.vhdl new file mode 100644 index 000000000..42127d7f9 --- /dev/null +++ b/testsuite/synth/slice01/slice04.vhdl @@ -0,0 +1,27 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity slice04 is + port (clk : std_logic; + dat : std_logic_vector (7 downto 0); + mask : std_logic_vector (1 downto 0); + res : out std_logic_vector (7 downto 0)); +end slice04; + +architecture behav of slice04 is + signal z : natural range 0 to 0; + signal mem : std_logic_vector (7 downto 0); +begin + z <= to_integer(unsigned(mask)); + + process(clk) + variable hi, lo : natural; + begin + if rising_edge (clk) then + mem (z*3 + 7 downto z*3) <= dat; + end if; + end process; + + res <= mem; +end behav; |